drivers/gpu/drm/via/via_crtc.c | 37 +++++++++++++++++++++----
drivers/gpu/drm/via/via_ioc32.c | 6 ++--
include/uapi/drm/via_drm.h | 57 ++++++++++++++++++----------------------
3 files changed, 61 insertions(+), 39 deletions(-)
New commits:
commit 649fe46010ade6389dc3825ad07599b9095ec7b4
Author: James Simmons <jsimm...@infradead.org>
Date: Sun Jul 21 09:22:59 2013 -0400
Update userland header according to reviews on drm-devel. Restored the
linux types and ensured it works on BSD. Since the only userland application is
the xorg driver it has a small impact.
diff --git a/drivers/gpu/drm/via/via_ioc32.c b/drivers/gpu/drm/via/via_ioc32.c
index 03b8508..156053b 100644
--- a/drivers/gpu/drm/via/via_ioc32.c
+++ b/drivers/gpu/drm/via/via_ioc32.c
@@ -63,7 +63,7 @@ via_gem_alloc(struct drm_device *dev, void *data,
struct drm_file *filp)
{
struct drm_via_private *dev_priv = dev->dev_private;
- struct drm_via_gem_create *args = data;
+ struct drm_via_gem_object *args = data;
struct drm_gem_object *obj;
int ret = -ENOMEM;
@@ -80,7 +80,7 @@ via_gem_alloc(struct drm_device *dev, void *data,
args->map_handle = bo->addr_space_offset;
args->offset = bo->offset;
args->size = bo->mem.size;
-
+ args->version = 1;
obj->read_domains = obj->write_domain = args->domains;
}
}
@@ -91,7 +91,7 @@ static int
via_gem_state(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
struct ttm_buffer_object *bo = NULL;
- struct drm_via_gem_create *args = data;
+ struct drm_via_gem_object *args = data;
struct drm_gem_object *obj = NULL;
struct ttm_placement placement;
int ret = -EINVAL;
diff --git a/include/uapi/drm/via_drm.h b/include/uapi/drm/via_drm.h
index 73ccb10..b85b2ff 100644
--- a/include/uapi/drm/via_drm.h
+++ b/include/uapi/drm/via_drm.h
@@ -24,7 +24,7 @@
#ifndef _VIA_DRM_H_
#define _VIA_DRM_H_
-#include <drm/drm.h>
+#include "drm.h"
/* WARNING: These defines must be the same as what the Xserver uses.
* if you change them, you must change the defines in the Xserver.
@@ -89,7 +89,7 @@
#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT,
drm_via_fb_t)
#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT,
drm_via_init_t)
#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE +
DRM_VIA_DEC_FUTEX, drm_via_futex_t)
-#define DRM_IOCTL_VIA_OLD_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_OLD_GEM_CREATE, struct drm_via_gem_create)
+#define DRM_IOCTL_VIA_OLD_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_OLD_GEM_CREATE, struct drm_via_gem_object)
#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT,
drm_via_dma_init_t)
#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE +
DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
@@ -103,9 +103,9 @@
/* KMS ioctls */
#define DRM_IOCTL_VIA_GETPARAM DRM_IOR(DRM_COMMAND_BASE + DRM_VIA_GETPARAM,
struct drm_via_param)
#define DRM_IOCTL_VIA_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_SETPARAM,
struct drm_via_param)
-#define DRM_IOCTL_VIA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_GEM_CREATE, struct drm_via_gem_create)
+#define DRM_IOCTL_VIA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_GEM_CREATE, struct drm_via_gem_object)
#define DRM_IOCTL_VIA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_GEM_WAIT,
struct drm_via_gem_wait)
-#define DRM_IOCTL_VIA_GEM_STATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_GEM_STATE, struct drm_via_gem_create)
+#define DRM_IOCTL_VIA_GEM_STATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_VIA_GEM_STATE, struct drm_via_gem_object)
/* Indices into buf.Setup where various bits of state are mirrored per
* context and per buffer. These can be fired at the card as a unit,
@@ -128,19 +128,19 @@
#define VIA_MEM_UNKNOWN 4
typedef struct {
- uint32_t offset;
- uint32_t size;
+ __u32 offset;
+ __u32 size;
} drm_via_agp_t;
typedef struct {
- uint32_t offset;
- uint32_t size;
+ __u32 offset;
+ __u32 size;
} drm_via_fb_t;
typedef struct {
- uint32_t context;
- uint32_t type;
- uint32_t size;
+ __u32 context;
+ __u32 type;
+ __u32 size;
unsigned long index;
unsigned long offset;
} drm_via_mem_t;
@@ -162,9 +162,9 @@ typedef struct _drm_via_futex {
VIA_FUTEX_WAIT = 0x00,
VIA_FUTEX_WAKE = 0X01
} func;
- uint32_t ms;
- uint32_t lock;
- uint32_t val;
+ __u32 ms;
+ __u32 lock;
+ __u32 val;
} drm_via_futex_t;
typedef struct _drm_via_dma_init {
@@ -225,7 +225,7 @@ typedef struct _drm_via_cmdbuf_size {
VIA_CMDBUF_LAG = 0x02
} func;
int wait;
- uint32_t size;
+ __u32 size;
} drm_via_cmdbuf_size_t;
typedef enum {
@@ -250,8 +250,8 @@ enum drm_via_irqs {
struct drm_via_wait_irq_request {
unsigned irq;
via_irq_seq_type_t type;
- uint32_t sequence;
- uint32_t signal;
+ __u32 sequence;
+ __u32 signal;
};
typedef union drm_via_irqwait {
@@ -260,7 +260,7 @@ typedef union drm_via_irqwait {
} drm_via_irqwait_t;
typedef struct drm_via_blitsync {
- uint32_t sync_handle;
+ __u32 sync_handle;
unsigned engine;
} drm_via_blitsync_t;
@@ -271,16 +271,16 @@ typedef struct drm_via_blitsync {
*/
typedef struct drm_via_dmablit {
- uint32_t num_lines;
- uint32_t line_length;
+ __u32 num_lines;
+ __u32 line_length;
- uint32_t fb_addr;
- uint32_t fb_stride;
+ __u32 fb_addr;
+ __u32 fb_stride;
unsigned char *mem_addr;
- uint32_t mem_stride;
+ __u32 mem_stride;
- int bounce_buffer;
+ __u32 flags;
int to_fb;
drm_via_blitsync_t sync;
@@ -296,7 +296,7 @@ struct drm_via_param {
uint64_t value;
};
-struct drm_via_gem_create {
+struct drm_via_gem_object {
/**
* Requested size for the object.
*
@@ -342,12 +342,9 @@ struct drm_via_gem_create {
uint32_t handle;
/**
- * Padding for future expansion.
+ * Version to tell how to handle this data.
*/
- uint32_t pad1;
- uint64_t pad2;
- uint64_t pad3;
- uint64_t pad4;
+ uint32_t version;
};
struct drm_via_gem_wait {
commit bb0e7927cea1666eacee4958ff8476dbcd4de685
Author: James Simmons <jsimm...@infradead.org>
Date: Sat Jul 20 19:27:41 2013 -0400
Was sending the wrong values to the pixel timings for when HDMI is on IGA 1.
diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index 79f320a..9de64ea 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -412,38 +412,63 @@ void via_load_crtc_pixel_timing(struct drm_crtc *crtc,
struct drm_display_mode *
reg_value = IGA1_PIXELTIMING_HOR_TOTAL_FORMULA(mode->crtc_htotal);
load_value_to_registers(VGABASE, &iga->pixel_timings.htotal, reg_value);
- reg_value = IGA1_PIXELTIMING_HOR_ADDR_FORMULA(mode->crtc_hdisplay);
+ reg_value = IGA1_PIXELTIMING_HOR_ADDR_FORMULA(mode->crtc_hdisplay) <<
16;
load_value_to_registers(VGABASE, &iga->pixel_timings.hdisplay,
reg_value);
reg_value =
IGA1_PIXELTIMING_HOR_BLANK_START_FORMULA(mode->crtc_hblank_start);
load_value_to_registers(VGABASE, &iga->pixel_timings.hblank_start,
reg_value);
- reg_value =
IGA1_PIXELTIMING_HOR_BLANK_END_FORMULA(mode->crtc_hblank_end);
+ reg_value =
IGA1_PIXELTIMING_HOR_BLANK_END_FORMULA(mode->crtc_hblank_end) << 16;
load_value_to_registers(VGABASE, &iga->pixel_timings.hblank_end,
reg_value);
reg_value =
IGA1_PIXELTIMING_HOR_SYNC_START_FORMULA(mode->crtc_hsync_start);
load_value_to_registers(VGABASE, &iga->pixel_timings.hsync_start,
reg_value);
- reg_value = IGA1_PIXELTIMING_HOR_SYNC_END_FORMULA(mode->crtc_hsync_end);
+ reg_value = IGA1_PIXELTIMING_HOR_SYNC_END_FORMULA(mode->crtc_hsync_end)
<< 16;
load_value_to_registers(VGABASE, &iga->pixel_timings.hsync_end,
reg_value);
reg_value = IGA1_PIXELTIMING_VER_TOTAL_FORMULA(mode->crtc_vtotal);
load_value_to_registers(VGABASE, &iga->pixel_timings.vtotal, reg_value);
- reg_value = IGA1_PIXELTIMING_VER_ADDR_FORMULA(mode->crtc_vdisplay);
+ reg_value = IGA1_PIXELTIMING_VER_ADDR_FORMULA(mode->crtc_vdisplay) <<
16;
load_value_to_registers(VGABASE, &iga->pixel_timings.vdisplay,
reg_value);
reg_value =
IGA1_PIXELTIMING_VER_BLANK_START_FORMULA(mode->crtc_vblank_start);
load_value_to_registers(VGABASE, &iga->pixel_timings.vblank_start,
reg_value);
- reg_value =
IGA1_PIXELTIMING_VER_BLANK_END_FORMULA(mode->crtc_vblank_end);
+ reg_value =
IGA1_PIXELTIMING_VER_BLANK_END_FORMULA(mode->crtc_vblank_end) << 16;
load_value_to_registers(VGABASE, &iga->pixel_timings.vblank_end,
reg_value);
reg_value =
IGA1_PIXELTIMING_VER_SYNC_START_FORMULA(mode->crtc_vsync_start);
load_value_to_registers(VGABASE, &iga->pixel_timings.vsync_start,
reg_value);
- reg_value = IGA1_PIXELTIMING_VER_SYNC_END_FORMULA(mode->crtc_vsync_end);
+ reg_value = IGA1_PIXELTIMING_VER_SYNC_END_FORMULA(mode->crtc_vsync_end)
<< 12;
load_value_to_registers(VGABASE, &iga->pixel_timings.vsync_end,
reg_value);
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ reg_value = IGA1_PIXELTIMING_HVSYNC_OFFSET_END_FORMULA
+ (mode->crtc_htotal, mode->crtc_hsync_start);
+ VIA_WRITE_MASK(IGA1_PIX_HALF_LINE_REG, reg_value,
+ IGA1_PIX_HALF_LINE_MASK);
+
+ svga_wcrt_mask(VGABASE, 0x32, BIT(2), BIT(2));
+ /**
+ * According to information from HW team,
+ * we need to set 0xC280[1] = 1 (HDMI function enable)
+ * or 0xC640[0] = 1 (DP1 enable)
+ * to let the half line function work.
+ * Otherwise, the clock for interlace mode
+ * will not correct.
+ * This is a special setting for 410.
+ */
+ VIA_WRITE_MASK(0xC280, BIT(1), BIT(1));
+ } else {
+ VIA_WRITE_MASK(IGA1_PIX_HALF_LINE_REG, 0x0,
+ IGA1_PIX_HALF_LINE_MASK);
+ svga_wcrt_mask(VGABASE, 0x32, 0x00, BIT(2));
+
+ }
+ svga_wcrt_mask(VGABASE, 0xFD, BIT(5) | BIT(6), BIT(5) | BIT(6));
}
/* Load CRTC timing registers */
_______________________________________________
Openchrome-devel mailing list
Openchrome-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/openchrome-devel
