configure.ac | 2
src/via_display.c | 18 ---
src/via_sii164.c | 277 +++++++++++++++++++++++++++++++++++++++++++++++++++---
src/via_vt1632.c | 277 +++++++++++++++++++++++++++++++++++++++++++++++++++---
4 files changed, 533 insertions(+), 41 deletions(-)
New commits:
commit 6f5b77320edd3ab1a644f2aa6e18db1d316944ba
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Sep 9 16:12:28 2016 -0700
Version bumped to 0.5.153
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index 44f5c16..f8bde36 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.5.152],
+ [0.5.153],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit 3ae673418b207c17fe452ba9ab524a60293a6d9d
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Sep 9 16:09:18 2016 -0700
Remove initialization of DVP0 from viaIGA2Init
The initialization of DVP0 will now be done at the code that initializes
the output device.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_display.c b/src/via_display.c
index e451f66..c8161c8 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -2367,24 +2367,6 @@ viaIGA2Init(ScrnInfoPtr pScrn)
* 1: Enable */
ViaCrtcMask(hwp, 0x79, 0x00, 0x01);
- /* Set DVP0 (Digital Video Port 0) source to IGA2. */
- /* 3X5.96[7] - DVP0 ALPHA Enable
- * 0: Disable
- * 1: Enable
- * 3X5.96[6] - DVP0 VSYNC Polarity
- * 0: Positive
- * 1: Negative
- * 3X5.96[5] - DVP0 HSYNC Polarity
- * 0: Positive
- * 1: Negative
- * 3X5.96[4] - DVP0 Data Source Selection 0
- * 0: Primary Display
- * 1: Secondary Display
- * 3X5.96[3] - DVP0 Clock Polarity
- * 3X5.96[2:0] - DVP0 Clock Adjust
- * Valid Value: 0 through 7 */
- ViaCrtcMask(hwp, 0x96, 0x10, 0x10);
-
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Exiting viaIGA2Init.\n"));
}
commit 32f146a8b6f0164ec0cce1124ee055d0b2fd8141
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Sep 9 16:02:31 2016 -0700
Improved SiI 164 display source and I/O pad initialization
This improvement affects CLE266 through P4M900 chipsets.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_sii164.c b/src/via_sii164.c
index ec69644..6cbc3c8 100644
--- a/src/via_sii164.c
+++ b/src/via_sii164.c
@@ -33,6 +33,270 @@
#include "via_sii164.h"
static void
+viaSiI164SetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource)
+{
+
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaSiI164SetDisplaySource.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DIP0 was not set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDisplaySource(pScrn, displaySource);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ viaDFPLowSetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDisplaySource(pScrn, displaySource);
+ } else if (!(sr12 & 0x10)) {
+ viaDFPLowSetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port
+ */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DVP1 is not set up for TMDS "
+ "transmitter use.\n");
+ }
+
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Unrecognized IGP for "
+ "TMDS transmitter use.\n");
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaSiI164SetDisplaySource.\n"));
+}
+
+static void
+viaSiI164EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
+{
+
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaSiI164EnableIOPads.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0EnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DIP0 was not set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0EnableIOPads(pScrn, ioPadState);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ viaDFPLowEnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0EnableIOPads(pScrn, ioPadState);
+ } else if (!(sr12 & 0x10)) {
+ viaDFPLowEnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port
+ */
+ if (!(sr13 & 0x40)) {
+ viaDVP1EnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DVP1 is not set up for TMDS "
+ "transmitter use.\n");
+ }
+
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Unrecognized IGP for "
+ "TMDS transmitter use.\n");
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaSiI164EnableIOPads.\n"));
+}
+
+static void
via_sii164_dump_registers(ScrnInfoPtr pScrn, I2CDevPtr pDev)
{
int i;
@@ -273,17 +537,8 @@ via_sii164_mode_set(xf86OutputPtr output, DisplayModePtr
mode,
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Entered via_sii164_mode_set.\n"));
- switch (pVia->Chipset) {
- case VIA_CX700:
- case VIA_VX800:
- case VIA_VX855:
- case VIA_VX900:
- viaDVP1SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
- viaDVP1EnableIOPads(pScrn, 0x03);
- break;
- default:
- break;
- }
+ viaSiI164SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
+ viaSiI164EnableIOPads(pScrn, 0x03);
via_sii164_dump_registers(pScrn, pSiI164Rec->SiI164I2CDev);
commit bd569c03883f2552fc168dd22285b8ab99bd5a39
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Fri Sep 9 15:40:19 2016 -0700
Improved VT1632(A) display source and I/O pad initialization
This improvement affects CLE266 through P4M900 chipsets.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_vt1632.c b/src/via_vt1632.c
index 59e7d08..6fb126c 100644
--- a/src/via_vt1632.c
+++ b/src/via_vt1632.c
@@ -33,6 +33,270 @@
#include "via_vt1632.h"
static void
+viaVT1632SetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource)
+{
+
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaVT1632SetDisplaySource.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DIP0 was not set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDisplaySource(pScrn, displaySource);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ viaDFPLowSetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDisplaySource(pScrn, displaySource);
+ } else if (!(sr12 & 0x10)) {
+ viaDFPLowSetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port
+ */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetDisplaySource(pScrn, displaySource);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DVP1 is not set up for TMDS "
+ "transmitter use.\n");
+ }
+
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Unrecognized IGP for "
+ "TMDS transmitter use.\n");
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaVT1632SetDisplaySource.\n"));
+}
+
+static void
+viaVT1632EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
+{
+
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaVT1632EnableIOPads.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0EnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DIP0 was not set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0EnableIOPads(pScrn, ioPadState);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ viaDFPLowEnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0EnableIOPads(pScrn, ioPadState);
+ } else if (!(sr12 & 0x10)) {
+ viaDFPLowEnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "None of the external ports were set up for "
+ "TMDS transmitter use.\n");
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port
+ */
+ if (!(sr13 & 0x40)) {
+ viaDVP1EnableIOPads(pScrn, ioPadState);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "DVP1 is not set up for TMDS "
+ "transmitter use.\n");
+ }
+
+ break;
+ default:
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Unrecognized IGP for "
+ "TMDS transmitter use.\n");
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaVT1632EnableIOPads.\n"));
+}
+
+static void
via_vt1632_dump_registers(ScrnInfoPtr pScrn, I2CDevPtr pDev)
{
int i;
@@ -286,17 +550,8 @@ via_vt1632_mode_set(xf86OutputPtr output, DisplayModePtr
mode,
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Entered via_vt1632_mode_set.\n"));
- switch (pVia->Chipset) {
- case VIA_CX700:
- case VIA_VX800:
- case VIA_VX855:
- case VIA_VX900:
- viaDVP1SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
- viaDVP1EnableIOPads(pScrn, 0x03);
- break;
- default:
- break;
- }
+ viaVT1632SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
+ viaVT1632EnableIOPads(pScrn, 0x03);
via_vt1632_dump_registers(pScrn, pVIAVT1632Rec->VT1632I2CDev);
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