configure.ac | 2
src/via_display.c | 237 ++++++++++++++++++++++++------------------------------
src/via_outputs.c | 4
src/via_tv.c | 8 -
src/via_ums.h | 1
src/via_vt1632.c | 16 +--
6 files changed, 123 insertions(+), 145 deletions(-)
New commits:
commit fa16bcf077c8f78c3b884b14bd4bfdbd037eadc4
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Sep 17 13:21:33 2016 -0700
Version bumped to 0.5.155
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index 16c34e9..79eb718 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.5.154],
+ [0.5.155],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit 30cd7cd0b71da188ff29fb212a0afa97207a6709
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Sep 17 13:20:21 2016 -0700
Improvement in standard VGA register initialization
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_display.c b/src/via_display.c
index 97e3646..0d4423b 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -429,44 +429,6 @@ ViaDisplaySetStreamOnDFP(ScrnInfoPtr pScrn, Bool primary)
ViaCrtcMask(hwp, 0x99, 0x10, 0x10);
}
-static void
-ViaCRTCSetGraphicsRegisters(ScrnInfoPtr pScrn)
-{
- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- /* graphics registers */
- hwp->writeGr(hwp, 0x00, 0x00);
- hwp->writeGr(hwp, 0x01, 0x00);
- hwp->writeGr(hwp, 0x02, 0x00);
- hwp->writeGr(hwp, 0x03, 0x00);
- hwp->writeGr(hwp, 0x04, 0x00);
- hwp->writeGr(hwp, 0x05, 0x40);
- hwp->writeGr(hwp, 0x06, 0x05);
- hwp->writeGr(hwp, 0x07, 0x0F);
- hwp->writeGr(hwp, 0x08, 0xFF);
-
- ViaGrMask(hwp, 0x20, 0, 0xFF);
- ViaGrMask(hwp, 0x21, 0, 0xFF);
- ViaGrMask(hwp, 0x22, 0, 0xFF);
-}
-
-static void
-ViaCRTCSetAttributeRegisters(ScrnInfoPtr pScrn)
-{
- vgaHWPtr hwp = VGAHWPTR(pScrn);
- CARD8 i;
-
- /* attribute registers */
- for (i = 0; i <= 0xF; i++) {
- hwp->writeAttr(hwp, i, i);
- }
- hwp->writeAttr(hwp, 0x10, 0x41);
- hwp->writeAttr(hwp, 0x11, 0xFF);
- hwp->writeAttr(hwp, 0x12, 0x0F);
- hwp->writeAttr(hwp, 0x13, 0x00);
- hwp->writeAttr(hwp, 0x14, 0x00);
-}
-
void
VIALoadRgbLut(ScrnInfoPtr pScrn, int start, int numColors, LOCO *colors)
{
@@ -543,17 +505,6 @@ ViaGammaDisable(ScrnInfoPtr pScrn)
}
}
-void
-ViaCRTCInit(ScrnInfoPtr pScrn)
-{
- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- hwp->writeSeq(hwp, 0x10, 0x01); /* unlock extended registers */
- ViaCrtcMask(hwp, 0x47, 0x00, 0x01); /* unlock CRT registers */
- ViaCRTCSetGraphicsRegisters(pScrn);
- ViaCRTCSetAttributeRegisters(pScrn);
-}
-
/*
* Initialize common IGA (Integrated Graphics Accelerator) registers.
*/
@@ -562,6 +513,7 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 i;
#ifdef HAVE_DEBUG
CARD8 temp;
#endif
@@ -569,12 +521,6 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Entered viaIGAInitCommon.\n"));
- /* Unlock VIA Technologies extended VGA registers. */
- /* 3C5.10[0] - Unlock Accessing of I/O Space
- * 0: Disable
- * 1: Enable */
- ViaSeqMask(hwp, 0x10, 0x01, 0x01);
-
temp = hwp->readEnable(hwp);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Enable Register: 0x%02X\n", temp));
@@ -583,7 +529,7 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readMiscOut(hwp);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Misc. Register: 0x%02X\n", temp));
- hwp->writeMiscOut(hwp, temp | 0x2E);
+ hwp->writeMiscOut(hwp, temp | 0x22);
temp = hwp->readEnable(hwp);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -592,8 +538,89 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Misc. Register: 0x%02X\n", temp));
- ViaCRTCSetGraphicsRegisters(pScrn);
- ViaCRTCSetAttributeRegisters(pScrn);
+
+ /* Sequencer Registers */
+ ViaSeqMask(hwp, 0x00, 0x03, 0x03);
+ ViaSeqMask(hwp, 0x01, 0x01, 0x35);
+ ViaSeqMask(hwp, 0x02, 0x0F, 0x0F);
+ ViaSeqMask(hwp, 0x03, 0x00, 0x3F);
+ ViaSeqMask(hwp, 0x04, 0x0E, 0x0E);
+
+
+ /* Graphics Registers */
+ hwp->writeGr(hwp, 0x00, 0x00);
+ hwp->writeGr(hwp, 0x01, 0x00);
+ hwp->writeGr(hwp, 0x02, 0x00);
+ hwp->writeGr(hwp, 0x03, 0x00);
+ hwp->writeGr(hwp, 0x04, 0x00);
+ hwp->writeGr(hwp, 0x05, 0x40);
+ hwp->writeGr(hwp, 0x06, 0x05);
+ hwp->writeGr(hwp, 0x07, 0x0F);
+ hwp->writeGr(hwp, 0x08, 0xFF);
+
+
+ /* Attribute Registers */
+ for (i = 0; i <= 15; i++) {
+ hwp->writeAttr(hwp, i, i);
+ }
+
+ hwp->writeAttr(hwp, 0x10, 0x41);
+ hwp->writeAttr(hwp, 0x11, 0xFF);
+ hwp->writeAttr(hwp, 0x12, 0x0F);
+ hwp->writeAttr(hwp, 0x13, 0x00);
+ hwp->writeAttr(hwp, 0x14, 0x00);
+
+
+ /* Unlock VIA Technologies extended VGA registers. */
+ /* 3C5.10[0] - Unlock Accessing of I/O Space
+ * 0: Disable
+ * 1: Enable */
+ ViaSeqMask(hwp, 0x10, 0x01, 0x01);
+
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ case VIA_CX700:
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ case VIA_VX800:
+ /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
+ * 3X5.47[6] - IGA1 Timing Plus 4 VCK
+ * 3X5.47[5] - Peep at the PCI-bus
+ * 0: Disable
+ * 1: Enable
+ * 3X5.47[4] - Reserved
+ * 3X5.47[3] - IGA1 Timing Plus 6 VCK
+ * 3X5.47[2] - DACOFF Backdoor Register
+ * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
+ * 8/9 Dot Clocks
+ * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
+ * Clock Select and CRTC Register Protect */
+ ViaCrtcMask(hwp, 0x47, 0x00, 0x01);
+ break;
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
+ * 3X5.47[6] - IGA1 Timing Plus 4 VCK
+ * 3X5.47[5] - Peep at the PCI-bus
+ * 0: Disable
+ * 1: Enable
+ * 3X5.47[4] - CRT Timing Register Protect
+ * 3X5.47[3] - IGA1 Timing Plus 6 VCK
+ * 3X5.47[2] - DACOFF Backdoor Register
+ * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
+ * 8/9 Dot Clocks
+ * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
+ * Clock Select */
+ ViaCrtcMask(hwp, 0x47, 0x00, 0x10);
+ break;
+ default:
+ break;
+ }
#ifdef HAVE_DEBUG
temp = hwp->readSeq(hwp, 0x15);
@@ -623,15 +650,9 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readCrtc(hwp, 0x36);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR36: 0x%02X\n", temp));
-
- /* For UniChrome Pro and Chrome9. */
- if ((pVia->Chipset != VIA_CLE266)
- && (pVia->Chipset != VIA_KM400)) {
- temp = hwp->readCrtc(hwp, 0x47);
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "CR47: 0x%02X\n", temp));
- }
-
+ temp = hwp->readCrtc(hwp, 0x47);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "CR47: 0x%02X\n", temp));
temp = hwp->readCrtc(hwp, 0x6B);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR6B: 0x%02X\n", temp));
@@ -644,6 +665,13 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
#endif
+
+ /* VIA Technologies Chrome Extended Graphics Registers */
+ ViaGrMask(hwp, 0x20, 0, 0xFF);
+ ViaGrMask(hwp, 0x21, 0, 0xFF);
+ ViaGrMask(hwp, 0x22, 0, 0xFF);
+
+
/* Be careful with 3C5.15[5] - Wrap Around Disable.
* It must be set to 1 for correct operation. */
/* 3C5.15[7] - 8/6 Bits LUT
@@ -815,52 +843,14 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* 1: Enable */
ViaCrtcMask(hwp, 0x36, 0x01, 0x01);
- switch (pVia->Chipset) {
- case VIA_CLE266:
- case VIA_KM400:
- ViaCrtcMask(hwp, 0x47, 0x00, 0x23);
- break;
- case VIA_K8M800:
- case VIA_PM800:
- case VIA_P4M800PRO:
- case VIA_CX700:
- case VIA_P4M890:
- case VIA_K8M890:
- case VIA_P4M900:
- case VIA_VX800:
- /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
- * 3X5.47[6] - IGA1 Timing Plus 4 VCK
- * 3X5.47[5] - Peep at the PCI-bus
- * 0: Disable
- * 1: Enable
- * 3X5.47[4] - Reserved
- * 3X5.47[3] - IGA1 Timing Plus 6 VCK
- * 3X5.47[2] - DACOFF Backdoor Register
- * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
- * 8/9 Dot Clocks
- * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
- * Clock Select and CRTC Register Protect */
- ViaCrtcMask(hwp, 0x47, 0x00, 0x23);
- break;
- case VIA_VX855:
- case VIA_VX900:
- /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
- * 3X5.47[6] - IGA1 Timing Plus 4 VCK
- * 3X5.47[5] - Peep at the PCI-bus
- * 0: Disable
- * 1: Enable
- * 3X5.47[4] - CRT Timing Register Protect
- * 3X5.47[3] - IGA1 Timing Plus 6 VCK
- * 3X5.47[2] - DACOFF Backdoor Register
- * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
- * 8/9 Dot Clocks
- * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
- * Clock Select */
- ViaCrtcMask(hwp, 0x47, 0x00, 0x33);
- break;
- default:
- break;
- }
+ /* 3X5.47[5] - Peep at the PCI-bus
+ * 0: Disable
+ * 1: Enable
+ * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
+ * 8/9 Dot Clocks
+ * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
+ * Clock Select and CRTC Register Protect */
+ ViaCrtcMask(hwp, 0x47, 0x00, 0x23);
/* 3X5.6B[3] - Simultaneous Display Enable
* 0: Disable
@@ -1164,20 +1154,11 @@ viaIGA1SetDisplayRegister(ScrnInfoPtr pScrn,
DisplayModePtr mode)
hwp->writeMiscOut(hwp, temp);
-
- /* Sequence registers */
- hwp->writeSeq(hwp, 0x00, 0x00);
-
-#if 0
- if (mode->Flags & V_CLKDIV2)
- hwp->writeSeq(hwp, 0x01, 0x09);
- else
-#endif
- hwp->writeSeq(hwp, 0x01, 0x01);
-
- hwp->writeSeq(hwp, 0x02, 0x0F);
- hwp->writeSeq(hwp, 0x03, 0x00);
- hwp->writeSeq(hwp, 0x04, 0x0E);
+ if (mode->Flags & V_CLKDIV2) {
+ ViaSeqMask(hwp, 0x01, 0x08, 0x08);
+ } else {
+ ViaSeqMask(hwp, 0x01, 0x00, 0x08);
+ }
ViaCrtcMask(hwp, 0x03, 0x80, 0x80); /* enable vertical retrace access */
@@ -3221,7 +3202,6 @@ iga1_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
viaIGAInitCommon(pScrn);
viaIGA1Init(pScrn);
- ViaCRTCInit(pScrn);
/* Turn off Screen */
ViaCrtcMask(hwp, 0x17, 0x00, 0x80);
@@ -3604,7 +3584,6 @@ iga2_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
viaIGAInitCommon(pScrn);
viaIGA2Init(pScrn);
- ViaCRTCInit(pScrn);
ViaPrintMode(pScrn, adjusted_mode);
viaIGA2SetDisplayRegister(pScrn, adjusted_mode);
diff --git a/src/via_ums.h b/src/via_ums.h
index 60a72e9..8e1e9af 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -243,7 +243,6 @@ void viaIGA2DisplayOutput(ScrnInfoPtr pScrn, Bool
outputState);
void viaIGA2DisplayChannel(ScrnInfoPtr pScrn, Bool channelState);
void viaDisplayInit(ScrnInfoPtr pScrn);
void ViaGammaDisable(ScrnInfoPtr pScrn);
-void ViaCRTCInit(ScrnInfoPtr pScrn);
void viaIGAInitCommon(ScrnInfoPtr pScrn);
void viaIGA1Init(ScrnInfoPtr pScrn);
void viaIGA1SetFBStartingAddress(xf86CrtcPtr crtc, int x, int y);
commit 1ab304a9c23d7abfcbc035859c52933c5dc9e0de
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sun Sep 11 00:49:48 2016 -0700
Changed via_vt1632_dump_registers to viaVT1632DumpRegisters
Also, made small changes to the log messages.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_vt1632.c b/src/via_vt1632.c
index 81559a7..ba866d6 100644
--- a/src/via_vt1632.c
+++ b/src/via_vt1632.c
@@ -497,22 +497,22 @@ viaVT1632SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8
dataDriveStrength)
}
static void
-via_vt1632_dump_registers(ScrnInfoPtr pScrn, I2CDevPtr pDev)
+viaVT1632DumpRegisters(ScrnInfoPtr pScrn, I2CDevPtr pDev)
{
int i;
CARD8 tmp;
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Entered via_vt1632_dump_registers.\n"));
+ "Entered viaVT1632DumpRegisters.\n"));
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VT1632A: dumping
registers:\n"));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dumping VT1632(A)
registers.\n"));
for (i = 0; i <= 0x0f; i++) {
xf86I2CReadByte(pDev, i, &tmp);
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VT1632A: 0x%02x:
0x%02x\n", i, tmp));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%02x: 0x%02x\n", i,
tmp));
}
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Exiting via_vt1632_dump_registers.\n"));
+ "Exiting viaVT1632DumpRegisters.\n"));
}
static void
@@ -755,11 +755,11 @@ via_vt1632_mode_set(xf86OutputPtr output, DisplayModePtr
mode,
viaVT1632SetClockDriveStrength(pScrn, 0x03);
viaVT1632SetDataDriveStrength(pScrn, 0x03);
- via_vt1632_dump_registers(pScrn, pVIAVT1632Rec->VT1632I2CDev);
+ viaVT1632DumpRegisters(pScrn, pVIAVT1632Rec->VT1632I2CDev);
viaVT1632InitRegisters(pScrn, pVIAVT1632Rec->VT1632I2CDev);
- via_vt1632_dump_registers(pScrn, pVIAVT1632Rec->VT1632I2CDev);
+ viaVT1632DumpRegisters(pScrn, pVIAVT1632Rec->VT1632I2CDev);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Exiting via_vt1632_mode_set.\n"));
@@ -948,7 +948,7 @@ viaVT1632Init(ScrnInfoPtr pScrn, I2CBusPtr pI2CBus)
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;
- via_vt1632_dump_registers(pScrn, pI2CDevice);
+ viaVT1632DumpRegisters(pScrn, pI2CDevice);
pVia->numberDVI++;
status = TRUE;
commit 10666db104e7a2a8dec3bd8176f2adf0fb355e6e
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sun Sep 11 00:09:49 2016 -0700
Fixing incorrect logical AND
The previous way the if statements were written will cause
malfunctions.
Suggested-by: Benno Schulenberg <bensb...@justemail.net>
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_outputs.c b/src/via_outputs.c
index 6bd4415..4e91d52 100644
--- a/src/via_outputs.c
+++ b/src/via_outputs.c
@@ -490,7 +490,7 @@ viaProbePinStrapping(ScrnInfoPtr pScrn)
* 01: NTSC
* 10: PAL-N
* 11: PAL-NC */
- if ((!(sr13 & 0x08)) & (sr13 & 0x04)) {
+ if ((!(sr13 & 0x08)) && (sr13 & 0x04)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"NTSC for the TV encoder.\n");
} else {
@@ -553,7 +553,7 @@ viaProbePinStrapping(ScrnInfoPtr pScrn)
/* 3C5.12[4] - DVP0D4 pin strapping
* 0: Dual 12-bit FPDP (Flat Panel Display Port)
- * 1: 24-bit FPDP (Flat Panel Display Port) */
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
if (sr12 & 0x10) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"24-bit FPDP (Flat Panel Display Port) "
diff --git a/src/via_tv.c b/src/via_tv.c
index fd8c9a9..82dc358 100644
--- a/src/via_tv.c
+++ b/src/via_tv.c
@@ -102,7 +102,7 @@ viaTVSetDisplaySource(ScrnInfoPtr pScrn, CARD8
displaySource)
* 1: DVP0 is used by a TV encoder
* 3C5.12[4] - DVP0D4 pin strapping
* 0: Dual 12-bit FPDP (Flat Panel Display Port)
- * 1: 24-bit FPDP (Flat Panel Display Port) */
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
if ((sr12 & 0x40) && (sr12 & 0x20)) {
viaDVP0SetDisplaySource(pScrn, displaySource);
} else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
@@ -127,8 +127,8 @@ viaTVSetDisplaySource(ScrnInfoPtr pScrn, CARD8
displaySource)
* 1: DVP0 is used by a TV encoder
* 3C5.12[4] - FPD4 pin strapping
* 0: Dual 12-bit FPDP (Flat Panel Display Port)
- * 1: 24-bit FPDP (Flat Panel Display Port) */
- if ((sr12 & 0x40) & (sr12 & 0x20) &(!(sr12 & 0x10))) {
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (sr12 & 0x20) && (!(sr12 & 0x10))) {
viaDVP0SetDisplaySource(pScrn, displaySource);
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -262,7 +262,7 @@ viaTVEnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
* 3C5.12[4] - FPD4 pin strapping
* 0: Dual 12-bit FPDP (Flat Panel Display Port)
* 1: 24-bit FPDP (Flat Panel Display Port) */
- if ((sr12 & 0x40) & (sr12 & 0x20) &(!(sr12 & 0x10))) {
+ if ((sr12 & 0x40) && (sr12 & 0x20) && (!(sr12 & 0x10))) {
viaDVP0EnableIOPads(pScrn, ioPadState);
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
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