drivers/gpu/drm/openchrome/via_crtc.c     |   20 ++++++++++----------
 drivers/gpu/drm/openchrome/via_disp_reg.h |    4 ++--
 drivers/gpu/drm/openchrome/via_drv.h      |    4 ++--
 3 files changed, 14 insertions(+), 14 deletions(-)

New commits:
commit 54ca9d799e1785c0a4996172f00c38ef5b4f0146
Author: Kevin Brace <kevinbr...@gmx.com>
Date:   Sun Jan 28 12:33:38 2018 -0800

    drm/openchrome: Version bumped to 3.0.71
    
    An important CLE266 chipset display regression fix got implemented. The
    correct functionality was validated on VIA EPIA-M mainboard. Standby
    resume (ACPI S3 State resume) is also working for EPIA-M now.
    
    Signed-off-by: Kevin Brace <kevinbr...@gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_drv.h 
b/drivers/gpu/drm/openchrome/via_drv.h
index cdb7c9ec8464..dd226148462d 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
 #define DRIVER_AUTHOR       "OpenChrome Project"
 #define DRIVER_NAME         "openchrome"
 #define DRIVER_DESC         "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE         "20171222"
+#define DRIVER_DATE         "20180128"
 
 #define DRIVER_MAJOR           3
 #define DRIVER_MINOR           0
-#define DRIVER_PATCHLEVEL      70
+#define DRIVER_PATCHLEVEL      71
 
 #include <linux/module.h>
 
commit 05a65791b356a3eddfb9dc045eaaf7d34eac5997
Author: Kevin Brace <kevinbr...@gmx.com>
Date:   Sat Jan 27 23:55:33 2018 -0800

    drm/openchrome: Cosmetic changes to display FIFO depth formula
    
    Signed-off-by: Kevin Brace <kevinbr...@gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_disp_reg.h 
b/drivers/gpu/drm/openchrome/via_disp_reg.h
index a3b2cf8ddcbe..e2bd895bb495 100644
--- a/drivers/gpu/drm/openchrome/via_disp_reg.h
+++ b/drivers/gpu/drm/openchrome/via_disp_reg.h
@@ -28,8 +28,8 @@
 /********************************************************/
 /* Definition IGA Design Method of FIFO Registers      */
 /********************************************************/
-#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)              ((x / 2) - 1)
-#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)              ((x / 2) / 4) - 1
+#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)              ((x >> 1) - 1)
+#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)              ((x >> 3) - 1)
 
 /* Define Display OFFSET */
 /* VT3314 chipset */
commit f37a2279a244114ce9a15dbf82f52c251b63adfa
Author: Kevin Brace <kevinbr...@gmx.com>
Date:   Sat Jan 27 23:50:04 2018 -0800

    drm/openchrome: KM400 IGA1 display FIFO parameter comment fix
    
    Signed-off-by: Kevin Brace <kevinbr...@gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_crtc.c 
b/drivers/gpu/drm/openchrome/via_crtc.c
index 20c4dca5f34f..6367c0d0f908 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -624,22 +624,22 @@ static void via_iga1_display_fifo_regs(struct drm_device 
*dev,
        case PCI_DEVICE_ID_VIA_KM400:
                if ((mode->hdisplay >= 1600) &&
                        (dev_priv->vram_type <= VIA_MEM_DDR_200)) {
-                       /* SR17[7:0] */
+                       /* SR17[6:0] */
                        fifo_max_depth = 58;
 
-                       /* SR16[7], SR16[5:0] */
+                       /* SR16[5:0] */
                        fifo_threshold = 24;
 
-                       /* SR18[7], SR18[5:0] */
+                       /* SR18[5:0] */
                        fifo_high_threshold = 92;
                } else {
-                       /* SR17[7:0] */
+                       /* SR17[6:0] */
                        fifo_max_depth = 128;
 
-                       /* SR16[7], SR16[5:0] */
+                       /* SR16[5:0] */
                        fifo_threshold = 112;
 
-                       /* SR18[7], SR18[5:0] */
+                       /* SR18[5:0] */
                        fifo_high_threshold = 92;
                }
 
commit ba307601f98b0c59c9380325a6c0a7d8a5173251
Author: Kevin Brace <kevinbr...@gmx.com>
Date:   Sat Jan 27 23:43:22 2018 -0800

    drm/openchrome: Fix for CLE266 IGA1 display regression
    
    The new CLE266 chipset IGA1 display FIFO parameters were severely
    disrupting IGA1 display. This commit fixes this bug. Also, with this
    fix, mode setting of IGA1 with analog (VGA) output after standby
    resumeis now fully working. This fix was validated on VIA EPIA-M
    mainboard.
    
    Signed-off-by: Kevin Brace <kevinbr...@gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_crtc.c 
b/drivers/gpu/drm/openchrome/via_crtc.c
index b5b667c9732a..20c4dca5f34f 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -505,7 +505,7 @@ static void via_iga1_display_fifo_regs(struct drm_device 
*dev,
                if (dev_priv->revision == CLE266_REVISION_AX) {
                        if (mode->hdisplay > 1024) {
                                /* SR17[6:0] */
-                               fifo_max_depth = 192;
+                               fifo_max_depth = 96;
 
                                /* SR16[5:0] */
                                fifo_threshold = 92;
@@ -516,7 +516,7 @@ static void via_iga1_display_fifo_regs(struct drm_device 
*dev,
                                enable_extended_display_fifo = true;
                        } else {
                                /* SR17[6:0] */
-                               fifo_max_depth = 128;
+                               fifo_max_depth = 64;
 
                                /* SR16[5:0] */
                                fifo_threshold = 32;
@@ -572,7 +572,7 @@ static void via_iga1_display_fifo_regs(struct drm_device 
*dev,
                } else {
                        if (mode->hdisplay >= 1024) {
                                /* SR17[6:0] */
-                               fifo_max_depth = 256;
+                               fifo_max_depth = 128;
 
                                /* SR16[5:0] */
                                fifo_threshold = 112;
@@ -583,7 +583,7 @@ static void via_iga1_display_fifo_regs(struct drm_device 
*dev,
                                enable_extended_display_fifo = false;
                        } else {
                                /* SR17[6:0] */
-                               fifo_max_depth = 128;
+                               fifo_max_depth = 64;
 
                                /* SR16[5:0] */
                                fifo_threshold = 32;
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