drivers/gpu/drm/openchrome/openchrome_crtc.c | 980 ++++++++++++---------------
drivers/gpu/drm/openchrome/openchrome_drv.h | 2
2 files changed, 438 insertions(+), 544 deletions(-)
New commits:
commit 166c1950bae86a2a45220fd6b9eb71f441363bc3
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:15:54 2019 -0700
drm/openchrome: Consolidate mode fixup code
It is being merged into openchrome_crtc_mode_fixup().
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index 7c1bffd25412..e3f8de6b4471 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -1582,6 +1582,16 @@ drm_mode_crtc_load_lut(struct drm_crtc *crtc)
}
}
+static bool openchrome_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return true;
+}
+
static int openchrome_crtc_mode_set_base(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb)
@@ -2022,17 +2032,6 @@ via_iga1_crtc_commit(struct drm_crtc *crtc)
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
}
-static bool
-via_iga1_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return true;
-}
-
static void
via_iga2_crtc_dpms(struct drm_crtc *crtc, int mode)
{
@@ -2099,24 +2098,13 @@ via_iga2_crtc_commit(struct drm_crtc *crtc)
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
}
-static bool
-via_iga2_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return true;
-}
-
static const struct
drm_crtc_helper_funcs openchrome_iga1_drm_crtc_helper_funcs = {
.dpms = via_iga1_crtc_dpms,
.disable = via_iga1_crtc_disable,
.prepare = via_iga1_crtc_prepare,
.commit = via_iga1_crtc_commit,
- .mode_fixup = via_iga1_crtc_mode_fixup,
+ .mode_fixup = openchrome_crtc_mode_fixup,
.mode_set = openchrome_crtc_mode_set,
.mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
@@ -2127,7 +2115,7 @@ drm_crtc_helper_funcs
openchrome_iga2_drm_crtc_helper_funcs = {
.disable = via_iga2_crtc_disable,
.prepare = via_iga2_crtc_prepare,
.commit = via_iga2_crtc_commit,
- .mode_fixup = via_iga2_crtc_mode_fixup,
+ .mode_fixup = openchrome_crtc_mode_fixup,
.mode_set = openchrome_crtc_mode_set,
.mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
commit 0fa5ca600bae4ded73890821352859f24453a36f
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:15:36 2019 -0700
drm/openchrome: Consolidate mode set code
It is being merged into openchrome_crtc_mode_set().
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index 31c62ce0b2e6..7c1bffd25412 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -1663,6 +1663,211 @@ exit:
return ret;
}
+static int openchrome_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *fb)
+{
+ struct via_crtc *iga = container_of(crtc,
+ struct via_crtc, base);
+ struct openchrome_drm_private *dev_private =
+ crtc->dev->dev_private;
+ struct drm_device *dev = crtc->dev;
+ u8 reg_value = 0;
+ int ret;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ if (!iga->index) {
+ /* Load standard registers */
+ via_load_vpit_regs(dev_private);
+
+ /* Unlock */
+ via_unlock_crtc(VGABASE, dev->pdev->device);
+
+ /* IGA1 reset */
+ vga_wcrt(VGABASE, 0x09, 0x00); /* initial CR09=0 */
+ svga_wcrt_mask(VGABASE, 0x11, 0x00, BIT(6));
+
+ /* disable IGA scales first */
+ via_disable_iga_scaling(crtc);
+
+ /*
+ * when not down scaling, we only need load one
+ * timing.
+ */
+ via_load_crtc_timing(iga, adjusted_mode);
+
+ switch (adjusted_mode->crtc_htotal % 8) {
+ case 0:
+ default:
+ break;
+ case 2:
+ reg_value = BIT(7);
+ break;
+ case 4:
+ reg_value = BIT(6);
+ break;
+ case 6:
+ reg_value = BIT(3);
+ break;
+ }
+
+ svga_wcrt_mask(VGABASE, 0x47,
+ reg_value, BIT(7) | BIT(6) | BIT(3));
+
+ /* Relock */
+ via_lock_crtc(VGABASE);
+
+ /* Set non-interlace / interlace mode. */
+ via_iga1_set_interlace_mode(VGABASE,
+ adjusted_mode->flags &
+ DRM_MODE_FLAG_INTERLACE);
+
+ /* No HSYNC shift. */
+ via_iga1_set_hsync_shift(VGABASE, 0x05);
+
+ /* Load display FIFO. */
+ ret = via_iga1_display_fifo_regs(dev, dev_private,
+ iga, adjusted_mode,
+ crtc->primary->fb);
+ if (ret) {
+ goto exit;
+ }
+
+ /* Set PLL */
+ if (adjusted_mode->clock) {
+ u32 clock = adjusted_mode->clock * 1000;
+ u32 pll_regs;
+
+ if (iga->scaling_mode & VIA_SHRINK)
+ clock *= 2;
+ pll_regs = via_get_clk_value(crtc->dev, clock);
+ via_set_vclock(crtc, pll_regs);
+ }
+ } else {
+ /* Load standard registers */
+ via_load_vpit_regs(dev_private);
+
+ /* Unlock */
+ via_unlock_crtc(VGABASE, dev->pdev->device);
+
+ /* disable IGA scales first */
+ via_disable_iga_scaling(crtc);
+
+ /* Load crtc timing and IGA scaling */
+ if (iga->scaling_mode & VIA_SHRINK) {
+ /*
+ * enable IGA2 down scaling and set
+ * Interpolation
+ */
+ via_set_iga_scale_function(crtc, VIA_SHRINK);
+
+ /* load hor and ver downscaling factor */
+ /*
+ * interlace modes scaling support(example
+ * 1080I): we should use mode->crtc_vdisplay
+ * here, because crtc_vdisplay=540,
+ * vdisplay=1080, we need 540 here, not 1080.
+ */
+ via_load_iga_scale_factor_regs(dev_private,
+ mode,
+ adjusted_mode,
+ VIA_SHRINK,
+ HOR_VER_SCALE);
+ /* load src timing to timing registers */
+ /*
+ * interlace modes scaling support(example
+ * 1080I): we should use mode->crtc_vdisplay
+ * here, because crtc_vdisplay=540,
+ * vdisplay=1080, we need 540 here, not 1080.
+ */
+ via_set_iga2_downscale_source_timing(crtc,
+ mode,
+ adjusted_mode);
+
+ /* Download dst timing */
+ via_set_scale_path(crtc, VIA_SHRINK);
+ via_load_crtc_timing(iga, adjusted_mode);
+ /*
+ * very necessary to set IGA to none scaling
+ * status need to fix why so need.
+ */
+ via_set_scale_path(crtc, VIA_NO_SCALING);
+ } else {
+ /*
+ * when not down scaling, we only need load
+ * one timing.
+ */
+ via_load_crtc_timing(iga, adjusted_mode);
+
+ /* II. up scaling */
+ if (iga->scaling_mode & VIA_EXPAND) {
+ /* Horizontal scaling */
+ if (iga->scaling_mode &
+ VIA_HOR_EXPAND) {
+ via_set_iga_scale_function(
+ crtc,
+ VIA_HOR_EXPAND);
+ via_load_iga_scale_factor_regs(
+ dev_private,
+ mode,
+ adjusted_mode,
+ VIA_EXPAND,
+ HOR_SCALE);
+ }
+
+ /* Vertical scaling */
+ if (iga->scaling_mode &
+ VIA_VER_EXPAND) {
+ via_set_iga_scale_function(
+ crtc,
+ VIA_VER_EXPAND);
+ via_load_iga_scale_factor_regs(
+ dev_private,
+ mode,
+ adjusted_mode,
+ VIA_EXPAND,
+ VER_SCALE);
+ }
+ }
+ }
+
+ /* Relock */
+ via_lock_crtc(VGABASE);
+
+ /* Set non-interlace / interlace mode. */
+ via_iga2_set_interlace_mode(VGABASE,
+ adjusted_mode->flags &
+ DRM_MODE_FLAG_INTERLACE);
+
+ /* Load display FIFO. */
+ ret = via_iga2_display_fifo_regs(dev, dev_private,
+ iga, adjusted_mode,
+ crtc->primary->fb);
+ if (ret) {
+ goto exit;
+ }
+
+ /* Set PLL */
+ if (adjusted_mode->clock) {
+ u32 clock = adjusted_mode->clock * 1000;
+ u32 pll_regs;
+
+ if (iga->scaling_mode & VIA_SHRINK)
+ clock *= 2;
+ pll_regs = via_get_clk_value(crtc->dev, clock);
+ via_set_vclock(crtc, pll_regs);
+ }
+ }
+
+ ret = openchrome_crtc_mode_set_base(crtc, x, y, fb);
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
+
static int openchrome_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y,
@@ -1828,95 +2033,6 @@ via_iga1_crtc_mode_fixup(struct drm_crtc *crtc,
return true;
}
-static int
-via_iga1_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y, struct drm_framebuffer *fb)
-{
- struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
- struct openchrome_drm_private *dev_private =
- crtc->dev->dev_private;
- struct drm_device *dev = crtc->dev;
- u8 reg_value = 0;
- int ret;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /* Check for IGA2. */
- if (iga->index) {
- DRM_ERROR("Wrong display controller (CRTC) selection.");
- ret = -EINVAL;
- goto exit;
- }
-
- /* Load standard registers */
- via_load_vpit_regs(dev_private);
-
- /* Unlock */
- via_unlock_crtc(VGABASE, dev->pdev->device);
-
- /* IGA1 reset */
- vga_wcrt(VGABASE, 0x09, 0x00); /* initial CR09=0 */
- svga_wcrt_mask(VGABASE, 0x11, 0x00, BIT(6));
-
- /* disable IGA scales first */
- via_disable_iga_scaling(crtc);
-
- /* when not down scaling, we only need load one timing. */
- via_load_crtc_timing(iga, adjusted_mode);
-
- switch (adjusted_mode->crtc_htotal % 8) {
- case 0:
- default:
- break;
- case 2:
- reg_value = BIT(7);
- break;
- case 4:
- reg_value = BIT(6);
- break;
- case 6:
- reg_value = BIT(3);
- break;
- }
-
- svga_wcrt_mask(VGABASE, 0x47, reg_value, BIT(7) | BIT(6) | BIT(3));
-
- /* Relock */
- via_lock_crtc(VGABASE);
-
- /* Set non-interlace / interlace mode. */
- via_iga1_set_interlace_mode(VGABASE,
- adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
-
- /* No HSYNC shift. */
- via_iga1_set_hsync_shift(VGABASE, 0x05);
-
- /* Load display FIFO. */
- ret = via_iga1_display_fifo_regs(dev, dev_private, iga,
- adjusted_mode,
- crtc->primary->fb);
- if (ret) {
- goto exit;
- }
-
- /* Set PLL */
- if (adjusted_mode->clock) {
- u32 clock = adjusted_mode->clock * 1000, pll_regs;
-
- if (iga->scaling_mode & VIA_SHRINK)
- clock *= 2;
- pll_regs = via_get_clk_value(crtc->dev, clock);
- via_set_vclock(crtc, pll_regs);
- }
-
- ret = openchrome_crtc_mode_set_base(crtc, x, y, fb);
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
static void
via_iga2_crtc_dpms(struct drm_crtc *crtc, int mode)
{
@@ -1994,127 +2110,6 @@ via_iga2_crtc_mode_fixup(struct drm_crtc *crtc,
return true;
}
-static int
-via_iga2_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode, struct drm_display_mode
*adjusted_mode,
- int x, int y, struct drm_framebuffer *fb)
-{
- struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
- struct openchrome_drm_private *dev_private =
- crtc->dev->dev_private;
- struct drm_device *dev = crtc->dev;
- int ret;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /* Check for IGA1. */
- if (!iga->index) {
- DRM_ERROR("Wrong display controller (CRTC) selection.");
- ret = -EINVAL;
- goto exit;
- }
-
- /* Load standard registers */
- via_load_vpit_regs(dev_private);
-
- /* Unlock */
- via_unlock_crtc(VGABASE, dev->pdev->device);
-
- /* disable IGA scales first */
- via_disable_iga_scaling(crtc);
-
- /* Load crtc timing and IGA scaling */
- if (iga->scaling_mode & VIA_SHRINK) {
- /* enable IGA2 down scaling and set Interpolation */
- via_set_iga_scale_function(crtc, VIA_SHRINK);
-
- /* load hor and ver downscaling factor */
- /**
- * interlace modes scaling support(example 1080I):
- * we should use mode->crtc_vdisplay here,
- * because crtc_vdisplay=540, vdisplay=1080,
- * we need 540 here, not 1080.
- */
- via_load_iga_scale_factor_regs(dev_private,
- mode, adjusted_mode,
- VIA_SHRINK,
- HOR_VER_SCALE);
- /* load src timing to timing registers */
- /**
- * interlace modes scaling support(example 1080I):
- * we should use mode->crtc_vdisplay here,
- * because crtc_vdisplay=540, vdisplay=1080,
- * we need 540 here, not 1080.
- */
- via_set_iga2_downscale_source_timing(crtc, mode, adjusted_mode);
-
- /* Download dst timing */
- via_set_scale_path(crtc, VIA_SHRINK);
- via_load_crtc_timing(iga, adjusted_mode);
- /* very necessary to set IGA to none scaling status */
- /* need to fix why so need. */
- via_set_scale_path(crtc, VIA_NO_SCALING);
- } else {
- /* when not down scaling, we only need load one timing. */
- via_load_crtc_timing(iga, adjusted_mode);
-
- /* II. up scaling */
- if (iga->scaling_mode & VIA_EXPAND) {
- /* Horizontal scaling */
- if (iga->scaling_mode & VIA_HOR_EXPAND) {
- via_set_iga_scale_function(crtc,
- VIA_HOR_EXPAND);
- via_load_iga_scale_factor_regs(
- dev_private,
- mode, adjusted_mode,
- VIA_EXPAND,
- HOR_SCALE);
- }
-
- /* Vertical scaling */
- if (iga->scaling_mode & VIA_VER_EXPAND) {
- via_set_iga_scale_function(crtc,
- VIA_VER_EXPAND);
- via_load_iga_scale_factor_regs(
- dev_private,
- mode, adjusted_mode,
- VIA_EXPAND,
- VER_SCALE);
- }
- }
- }
-
- /* Relock */
- via_lock_crtc(VGABASE);
-
- /* Set non-interlace / interlace mode. */
- via_iga2_set_interlace_mode(VGABASE,
- adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
-
- /* Load display FIFO. */
- ret = via_iga2_display_fifo_regs(dev, dev_private, iga,
- adjusted_mode,
- crtc->primary->fb);
- if (ret) {
- goto exit;
- }
-
- /* Set PLL */
- if (adjusted_mode->clock) {
- u32 clock = adjusted_mode->clock * 1000, pll_regs;
-
- if (iga->scaling_mode & VIA_SHRINK)
- clock *= 2;
- pll_regs = via_get_clk_value(crtc->dev, clock);
- via_set_vclock(crtc, pll_regs);
- }
-
- ret = openchrome_crtc_mode_set_base(crtc, x, y, fb);
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
static const struct
drm_crtc_helper_funcs openchrome_iga1_drm_crtc_helper_funcs = {
.dpms = via_iga1_crtc_dpms,
@@ -2122,7 +2117,7 @@ drm_crtc_helper_funcs
openchrome_iga1_drm_crtc_helper_funcs = {
.prepare = via_iga1_crtc_prepare,
.commit = via_iga1_crtc_commit,
.mode_fixup = via_iga1_crtc_mode_fixup,
- .mode_set = via_iga1_crtc_mode_set,
+ .mode_set = openchrome_crtc_mode_set,
.mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
@@ -2133,7 +2128,7 @@ drm_crtc_helper_funcs
openchrome_iga2_drm_crtc_helper_funcs = {
.prepare = via_iga2_crtc_prepare,
.commit = via_iga2_crtc_commit,
.mode_fixup = via_iga2_crtc_mode_fixup,
- .mode_set = via_iga2_crtc_mode_set,
+ .mode_set = openchrome_crtc_mode_set,
.mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
commit db13b2ec61ce4ec34900fc2207a52c77fd6d9cef
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:15:25 2019 -0700
drm/openchrome: Consolidate mode set base code
It is being merged into openchrome_crtc_mode_set_base().
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index cf9599fe311d..31c62ce0b2e6 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -1582,6 +1582,87 @@ drm_mode_crtc_load_lut(struct drm_crtc *crtc)
}
}
+static int openchrome_crtc_mode_set_base(struct drm_crtc *crtc,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct via_framebuffer *via_fb = container_of(
+ crtc->primary->fb,
+ struct via_framebuffer, fb);
+ struct drm_framebuffer *new_fb = &via_fb->fb;
+ struct openchrome_bo *bo;
+ struct drm_gem_object *gem;
+ int ret = 0;
+ int fake_ret = 0;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /* No FB found. */
+ if (!new_fb) {
+ ret = -ENOMEM;
+ DRM_DEBUG_KMS("No FB found.\n");
+ goto exit;
+ }
+
+ gem = via_fb->gem;
+ bo = container_of(gem, struct openchrome_bo, gem);
+
+ ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
+ if (ret) {
+ DRM_DEBUG_KMS("Failed to reserve FB.\n");
+ goto exit;
+ }
+
+ ret = openchrome_bo_pin(bo, TTM_PL_FLAG_VRAM);
+ ttm_bo_unreserve(&bo->ttm_bo);
+ if (ret) {
+ DRM_DEBUG_KMS("Failed to pin FB.\n");
+ goto exit;
+ }
+
+ ret = crtc->helper_private->mode_set_base_atomic(crtc,
+ new_fb, x, y,
+ ENTER_ATOMIC_MODE_SET);
+ if (unlikely(ret)) {
+ DRM_DEBUG_KMS("Failed to set a new FB.\n");
+ fake_ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
+ if (fake_ret) {
+ goto exit;
+ }
+
+ fake_ret = openchrome_bo_unpin(bo);
+ ttm_bo_unreserve(&bo->ttm_bo);
+ goto exit;
+ }
+
+ /*
+ * Free the old framebuffer if it exists.
+ */
+ if (old_fb) {
+ via_fb = container_of(old_fb,
+ struct via_framebuffer, fb);
+ gem = via_fb->gem;
+ bo = container_of(gem, struct openchrome_bo, gem);
+
+ ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
+ if (ret) {
+ DRM_DEBUG_KMS("FB still locked.\n");
+ goto exit;
+ }
+
+ ret = openchrome_bo_unpin(bo);
+ ttm_bo_unreserve(&bo->ttm_bo);
+ if (ret) {
+ DRM_DEBUG_KMS("FB still locked.\n");
+ goto exit;
+ }
+ }
+
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
+
static int openchrome_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y,
@@ -1748,86 +1829,6 @@ via_iga1_crtc_mode_fixup(struct drm_crtc *crtc,
}
static int
-via_iga1_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
-{
- struct via_framebuffer *via_fb = container_of(crtc->primary->fb,
- struct via_framebuffer, fb);
- struct drm_framebuffer *new_fb = &via_fb->fb;
- struct openchrome_bo *bo;
- struct drm_gem_object *gem;
- int ret = 0;
- int fake_ret = 0;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /* No FB found. */
- if (!new_fb) {
- ret = -ENOMEM;
- DRM_DEBUG_KMS("No FB found.\n");
- goto exit;
- }
-
- gem = via_fb->gem;
- bo = container_of(gem, struct openchrome_bo, gem);
-
- ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
- if (ret) {
- DRM_DEBUG_KMS("Failed to reserve FB.\n");
- goto exit;
- }
-
- ret = openchrome_bo_pin(bo, TTM_PL_FLAG_VRAM);
- ttm_bo_unreserve(&bo->ttm_bo);
- if (ret) {
- DRM_DEBUG_KMS("Failed to pin FB.\n");
- goto exit;
- }
-
- ret = crtc->helper_private->mode_set_base_atomic(crtc,
- new_fb, x, y,
- ENTER_ATOMIC_MODE_SET);
- if (unlikely(ret)) {
- DRM_DEBUG_KMS("Failed to set a new FB.\n");
- fake_ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
- if (fake_ret) {
- goto exit;
- }
-
- fake_ret = openchrome_bo_unpin(bo);
- ttm_bo_unreserve(&bo->ttm_bo);
- goto exit;
- }
-
- /*
- * Free the old framebuffer if it exists.
- */
- if (old_fb) {
- via_fb = container_of(old_fb,
- struct via_framebuffer, fb);
- gem = via_fb->gem;
- bo = container_of(gem, struct openchrome_bo, gem);
-
- ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
- if (ret) {
- DRM_DEBUG_KMS("FB still locked.\n");
- goto exit;
- }
-
- ret = openchrome_bo_unpin(bo);
- ttm_bo_unreserve(&bo->ttm_bo);
- if (ret) {
- DRM_DEBUG_KMS("FB still locked.\n");
- goto exit;
- }
- }
-
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
-static int
via_iga1_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -1910,7 +1911,7 @@ via_iga1_crtc_mode_set(struct drm_crtc *crtc,
via_set_vclock(crtc, pll_regs);
}
- ret = via_iga1_crtc_mode_set_base(crtc, x, y, fb);
+ ret = openchrome_crtc_mode_set_base(crtc, x, y, fb);
exit:
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
return ret;
@@ -1994,85 +1995,6 @@ via_iga2_crtc_mode_fixup(struct drm_crtc *crtc,
}
static int
-via_iga2_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
-{
- struct via_framebuffer *via_fb = container_of(crtc->primary->fb,
- struct via_framebuffer, fb);
- struct drm_framebuffer *new_fb = &via_fb->fb;
- struct openchrome_bo *bo;
- struct drm_gem_object *gem;
- int ret = 0;
- int fake_ret = 0;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /* No FB found. */
- if (!new_fb) {
- ret = -ENOMEM;
- DRM_DEBUG_KMS("No FB found.\n");
- goto exit;
- }
-
- gem = via_fb->gem;
- bo = container_of(gem, struct openchrome_bo, gem);
-
- ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
- if (ret) {
- DRM_DEBUG_KMS("Failed to reserve FB.\n");
- goto exit;
- }
-
- ret = openchrome_bo_pin(bo, TTM_PL_FLAG_VRAM);
- ttm_bo_unreserve(&bo->ttm_bo);
- if (ret) {
- DRM_DEBUG_KMS("Failed to pin FB.\n");
- goto exit;
- }
-
- ret = crtc->helper_private->mode_set_base_atomic(crtc, new_fb, x, y,
- ENTER_ATOMIC_MODE_SET);
- if (unlikely(ret)) {
- DRM_DEBUG_KMS("Failed to set a new FB.\n");
- fake_ret = ttm_bo_reserve(&bo->ttm_bo, true, false,
- NULL);
- if (fake_ret) {
- goto exit;
- }
-
- fake_ret = openchrome_bo_unpin(bo);
- ttm_bo_unreserve(&bo->ttm_bo);
- goto exit;
- }
-
- /*
- * Free the old framebuffer if it exists.
- */
- if (old_fb) {
- via_fb = container_of(old_fb,
- struct via_framebuffer, fb);
- gem = via_fb->gem;
- bo = container_of(gem, struct openchrome_bo, gem);
- ret = ttm_bo_reserve(&bo->ttm_bo, true, false, NULL);
- if (ret) {
- DRM_DEBUG_KMS("FB still locked.\n");
- goto exit;
- }
-
- ret = openchrome_bo_unpin(bo);
- ttm_bo_unreserve(&bo->ttm_bo);
- if (ret) {
- DRM_DEBUG_KMS("FB still locked.\n");
- goto exit;
- }
- }
-
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
-static int
via_iga2_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode, struct drm_display_mode
*adjusted_mode,
int x, int y, struct drm_framebuffer *fb)
@@ -2187,7 +2109,7 @@ via_iga2_crtc_mode_set(struct drm_crtc *crtc,
via_set_vclock(crtc, pll_regs);
}
- ret = via_iga2_crtc_mode_set_base(crtc, x, y, fb);
+ ret = openchrome_crtc_mode_set_base(crtc, x, y, fb);
exit:
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
return ret;
commit 62d9922346b7c1d130e63b5ddb0fe383801471e8
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:14:36 2019 -0700
drm/openchrome: Consolidate mode set base atomic code
It is being merged into openchrome_crtc_mode_set_base_atomic().
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index 8c8b91eda519..cf9599fe311d 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -1582,6 +1582,94 @@ drm_mode_crtc_load_lut(struct drm_crtc *crtc)
}
}
+static int openchrome_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
+ struct drm_framebuffer *fb,
+ int x, int y,
+ enum mode_set_atomic state)
+{
+ u32 pitch = y * fb->pitches[0] +
+ ((x * fb->format->cpp[0] * 8) >> 3), addr;
+ struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
+ struct openchrome_drm_private *dev_private =
+ crtc->dev->dev_private;
+ struct via_framebuffer *via_fb = container_of(fb,
+ struct via_framebuffer, fb);
+ struct drm_gem_object *gem = via_fb->gem;
+ struct openchrome_bo *bo = container_of(gem,
+ struct openchrome_bo, gem);
+ int ret = 0;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ if ((fb->format->depth != 8) && (fb->format->depth != 16) &&
+ (fb->format->depth != 24)) {
+ ret = -EINVAL;
+ DRM_ERROR("Unsupported IGA%s Color Depth: %d bit\n",
+ (!iga->index) ? "1" : "2",
+ fb->format->depth);
+ goto exit;
+ }
+
+ if (!iga->index) {
+ via_iga_common_init(VGABASE);
+
+ /* Set palette LUT to 8-bit mode. */
+ via_iga1_set_palette_lut_resolution(VGABASE, true);
+
+ via_iga1_set_color_depth(dev_private, fb->format->depth);
+
+ /* Set the framebuffer offset */
+ addr = round_up(bo->ttm_bo.offset + pitch, 16) >> 1;
+ vga_wcrt(VGABASE, 0x0D, addr & 0xFF);
+ vga_wcrt(VGABASE, 0x0C, (addr >> 8) & 0xFF);
+ /* Yes order of setting these registers matters on some
hardware */
+ svga_wcrt_mask(VGABASE, 0x48, ((addr >> 24) & 0x1F), 0x1F);
+ vga_wcrt(VGABASE, 0x34, (addr >> 16) & 0xFF);
+
+ /* Load fetch count registers */
+ pitch = ALIGN(crtc->mode.hdisplay * (fb->format->cpp[0] * 8) >>
3, 16);
+ load_value_to_registers(VGABASE, &iga->fetch, pitch >> 4);
+
+ /* Set the primary pitch */
+ pitch = ALIGN(fb->pitches[0], 16);
+ /* Spec does not say that first adapter skips 3 bits but old
+ * code did it and seems to be reasonable in analogy to
+ * second adapter */
+ load_value_to_registers(VGABASE, &iga->offset, pitch >> 3);
+ } else {
+ via_iga_common_init(VGABASE);
+
+ /* Set palette LUT to 8-bit mode. */
+ via_iga2_set_palette_lut_resolution(VGABASE, true);
+
+ via_iga2_set_color_depth(dev_private, fb->format->depth);
+
+ /* Set the framebuffer offset */
+ addr = round_up(bo->ttm_bo.offset + pitch, 16);
+ /* Bits 9 to 3 of the frame buffer go into bits 7 to 1
+ * of the register. Bit 0 is for setting tile mode or
+ * linear mode. A value of zero sets it to linear mode */
+ vga_wcrt(VGABASE, 0x62, ((addr >> 3) & 0x7F) << 1);
+ vga_wcrt(VGABASE, 0x63, (addr >> 10) & 0xFF);
+ vga_wcrt(VGABASE, 0x64, (addr >> 18) & 0xFF);
+ svga_wcrt_mask(VGABASE, 0xA3, ((addr >> 26) & 0x07), 0x07);
+
+ /* Load fetch count registers */
+ pitch = ALIGN(crtc->mode.hdisplay * (fb->format->cpp[0] * 8) >>
3, 16);
+ load_value_to_registers(VGABASE, &iga->fetch, pitch >> 4);
+
+ /* Set secondary pitch */
+ pitch = ALIGN(fb->pitches[0], 16);
+ load_value_to_registers(VGABASE, &iga->offset, pitch >> 3);
+
+ enable_second_display_channel(VGABASE);
+ }
+
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
+
static void
via_iga1_crtc_dpms(struct drm_crtc *crtc, int mode)
{
@@ -1828,58 +1916,6 @@ exit:
return ret;
}
-static int
-via_iga1_mode_set_base_atomic(struct drm_crtc *crtc,
- struct drm_framebuffer *fb, int x, int y,
- enum mode_set_atomic state)
-{
- u32 pitch = y * fb->pitches[0] +
- ((x * fb->format->cpp[0] * 8) >> 3), addr;
- struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
- struct openchrome_drm_private *dev_private =
- crtc->dev->dev_private;
- struct via_framebuffer *via_fb = container_of(fb,
- struct via_framebuffer, fb);
- struct drm_gem_object *gem = via_fb->gem;
- struct openchrome_bo *bo = container_of(gem,
- struct openchrome_bo, gem);
-
- if ((fb->format->depth != 8) && (fb->format->depth != 16) &&
- (fb->format->depth != 24)) {
- DRM_ERROR("Unsupported IGA1 Color Depth: %d bit\n",
- fb->format->depth);
- return -EINVAL;
- }
-
- via_iga_common_init(VGABASE);
-
- /* Set palette LUT to 8-bit mode. */
- via_iga1_set_palette_lut_resolution(VGABASE, true);
-
- via_iga1_set_color_depth(dev_private, fb->format->depth);
-
- /* Set the framebuffer offset */
- addr = round_up(bo->ttm_bo.offset + pitch, 16) >> 1;
- vga_wcrt(VGABASE, 0x0D, addr & 0xFF);
- vga_wcrt(VGABASE, 0x0C, (addr >> 8) & 0xFF);
- /* Yes order of setting these registers matters on some hardware */
- svga_wcrt_mask(VGABASE, 0x48, ((addr >> 24) & 0x1F), 0x1F);
- vga_wcrt(VGABASE, 0x34, (addr >> 16) & 0xFF);
-
- /* Load fetch count registers */
- pitch = ALIGN(crtc->mode.hdisplay * (fb->format->cpp[0] * 8) >> 3, 16);
- load_value_to_registers(VGABASE, &iga->fetch, pitch >> 4);
-
- /* Set the primary pitch */
- pitch = ALIGN(fb->pitches[0], 16);
- /* Spec does not say that first adapter skips 3 bits but old
- * code did it and seems to be reasonable in analogy to
- * second adapter */
- load_value_to_registers(VGABASE, &iga->offset, pitch >> 3);
-
- return 0;
-}
-
static void
via_iga2_crtc_dpms(struct drm_crtc *crtc, int mode)
{
@@ -2157,59 +2193,6 @@ exit:
return ret;
}
-static int
-via_iga2_mode_set_base_atomic(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- int x, int y, enum mode_set_atomic state)
-{
- u32 pitch = y * fb->pitches[0] +
- ((x * fb->format->cpp[0] * 8) >> 3), addr;
- struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
- struct openchrome_drm_private *dev_private =
- crtc->dev->dev_private;
- struct via_framebuffer *via_fb = container_of(fb,
- struct via_framebuffer, fb);
- struct drm_gem_object *gem = via_fb->gem;
- struct openchrome_bo *bo = container_of(gem,
- struct openchrome_bo, gem);
-
- if ((fb->format->depth != 8) && (fb->format->depth != 16) &&
- (fb->format->depth != 24)) {
- DRM_ERROR("Unsupported IGA2 Color Depth: %d bit\n",
- fb->format->depth);
- return -EINVAL;
- }
-
- via_iga_common_init(VGABASE);
-
- /* Set palette LUT to 8-bit mode. */
- via_iga2_set_palette_lut_resolution(VGABASE, true);
-
- via_iga2_set_color_depth(dev_private, fb->format->depth);
-
- /* Set the framebuffer offset */
- addr = round_up(bo->ttm_bo.offset + pitch, 16);
- /* Bits 9 to 3 of the frame buffer go into bits 7 to 1
- * of the register. Bit 0 is for setting tile mode or
- * linear mode. A value of zero sets it to linear mode */
- vga_wcrt(VGABASE, 0x62, ((addr >> 3) & 0x7F) << 1);
- vga_wcrt(VGABASE, 0x63, (addr >> 10) & 0xFF);
- vga_wcrt(VGABASE, 0x64, (addr >> 18) & 0xFF);
- svga_wcrt_mask(VGABASE, 0xA3, ((addr >> 26) & 0x07), 0x07);
-
- /* Load fetch count registers */
- pitch = ALIGN(crtc->mode.hdisplay * (fb->format->cpp[0] * 8) >> 3, 16);
- load_value_to_registers(VGABASE, &iga->fetch, pitch >> 4);
-
- /* Set secondary pitch */
- pitch = ALIGN(fb->pitches[0], 16);
- load_value_to_registers(VGABASE, &iga->offset, pitch >> 3);
-
- enable_second_display_channel(VGABASE);
-
- return 0;
-}
-
static const struct
drm_crtc_helper_funcs openchrome_iga1_drm_crtc_helper_funcs = {
.dpms = via_iga1_crtc_dpms,
@@ -2218,7 +2201,7 @@ drm_crtc_helper_funcs
openchrome_iga1_drm_crtc_helper_funcs = {
.commit = via_iga1_crtc_commit,
.mode_fixup = via_iga1_crtc_mode_fixup,
.mode_set = via_iga1_crtc_mode_set,
- .mode_set_base_atomic = via_iga1_mode_set_base_atomic,
+ .mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
static const struct
@@ -2229,7 +2212,7 @@ drm_crtc_helper_funcs
openchrome_iga2_drm_crtc_helper_funcs = {
.commit = via_iga2_crtc_commit,
.mode_fixup = via_iga2_crtc_mode_fixup,
.mode_set = via_iga2_crtc_mode_set,
- .mode_set_base_atomic = via_iga2_mode_set_base_atomic,
+ .mode_set_base_atomic = openchrome_crtc_mode_set_base_atomic,
};
static const uint32_t openchrome_primary_formats[] = {
commit 4f2df65a12607a0aa110a853fe31d2682dda6c76
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:14:17 2019 -0700
drm/openchrome: Use uint32_t type for identifying which IGA is being used
IGA (Integrated Graphics Accelerator) is a VIA Technologies term for
a display engine. In DRM / KMS terminology, CRTC (Cathode Ray Tube
Controller) is the closest term for it.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.h
b/drivers/gpu/drm/openchrome/openchrome_drv.h
index 448e2570c3f2..d27469d32084 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.h
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.h
@@ -167,7 +167,7 @@ struct via_crtc {
struct vga_registers offset;
struct vga_registers fetch;
int scaling_mode;
- uint8_t index;
+ uint32_t index;
};
struct via_connector {
commit e15bbae9900242222074f24de2839cb94153b610
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:13:56 2019 -0700
drm/openchrome: Drop erroneous reference to 32 bit color depth
In the future, the code should test bpp (bits per pixel) rather than
color depth when determining the number of bytes a pixel might occupy.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index 1ad8e050bac9..8c8b91eda519 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -98,15 +98,13 @@ static void via_iga1_set_color_depth(
value |= BIT(4) | BIT(2);
break;
case 24:
- case 32:
value |= BIT(3) | BIT(2);
break;
default:
break;
}
- if ((depth == 8) || (depth == 16) ||
- (depth == 24) || (depth == 32)) {
+ if ((depth == 8) || (depth == 16) || (depth == 24)) {
/* 3C5.15[4] - Hi Color Mode Select
* 0: 555
* 1: 565
@@ -144,15 +142,13 @@ static void via_iga2_set_color_depth(
value = BIT(6);
break;
case 24:
- case 32:
value = BIT(7) | BIT(6);
break;
default:
break;
}
- if ((depth == 8) || (depth == 16) ||
- (depth == 24) || (depth == 32)) {
+ if ((depth == 8) || (depth == 16) || (depth == 24)) {
/* 3X5.67[7:6] - Display Color Depth Select
* 00: 8bpp
* 01: 16bpp
@@ -418,7 +414,7 @@ static int via_iga1_display_fifo_regs(
}
if (dev_private->vram_type <= VIA_MEM_DDR_200) {
- if (fb->format->depth == 32) {
+ if (fb->format->depth == 24) {
if (mode->hdisplay > 1024) {
if (mode->vdisplay > 768) {
/* SR22[4:0] */
@@ -565,7 +561,7 @@ static int via_iga1_display_fifo_regs(
/* SR18[7], SR18[5:0] */
fifo_high_threshold = 296;
- if ((fb->format->depth == 32) &&
+ if ((fb->format->depth == 24) &&
(mode->hdisplay >= 1400)) {
/* SR22[4:0] */
display_queue_expire_num = 64;
@@ -585,7 +581,7 @@ static int via_iga1_display_fifo_regs(
/* SR18[7], SR18[5:0] */
fifo_high_threshold = 64;
- if ((fb->format->depth == 32) &&
+ if ((fb->format->depth == 24) &&
(mode->hdisplay >= 1400)) {
/* SR22[4:0] */
display_queue_expire_num = 64;
@@ -849,10 +845,10 @@ static int via_iga2_display_fifo_regs(
enable_extended_display_fifo = true;
} else if (((mode->hdisplay > 1024) &&
- (fb->format->depth == 32) &&
+ (fb->format->depth == 24) &&
(dev_private->vram_type <= VIA_MEM_DDR_333)) ||
((mode->hdisplay == 1024) &&
- (fb->format->depth == 32) &&
+ (fb->format->depth == 24) &&
(dev_private->vram_type <= VIA_MEM_DDR_200))) {
/* CR68[7:4] */
fifo_max_depth = 104;
@@ -895,7 +891,7 @@ static int via_iga2_display_fifo_regs(
/* CR95[2:0], CR92[3:0] */
fifo_high_threshold = 296;
- if ((fb->format->depth == 32) &&
+ if ((fb->format->depth == 24) &&
(mode->hdisplay >= 1400)) {
/* CR94[6:0] */
display_queue_expire_num = 64;
@@ -915,7 +911,7 @@ static int via_iga2_display_fifo_regs(
/* CR95[2:0], CR92[3:0] */
fifo_high_threshold = 32;
- if ((fb->format->depth == 32) &&
+ if ((fb->format->depth == 24) &&
(mode->hdisplay >= 1400)) {
/* CR94[6:0] */
display_queue_expire_num = 64;
@@ -1849,7 +1845,7 @@ via_iga1_mode_set_base_atomic(struct drm_crtc *crtc,
struct openchrome_bo, gem);
if ((fb->format->depth != 8) && (fb->format->depth != 16) &&
- (fb->format->depth != 24) && (fb->format->depth != 32)) {
+ (fb->format->depth != 24)) {
DRM_ERROR("Unsupported IGA1 Color Depth: %d bit\n",
fb->format->depth);
return -EINVAL;
@@ -2178,7 +2174,7 @@ via_iga2_mode_set_base_atomic(struct drm_crtc *crtc,
struct openchrome_bo, gem);
if ((fb->format->depth != 8) && (fb->format->depth != 16) &&
- (fb->format->depth != 24) && (fb->format->depth != 32)) {
+ (fb->format->depth != 24)) {
DRM_ERROR("Unsupported IGA2 Color Depth: %d bit\n",
fb->format->depth);
return -EINVAL;
commit 349a46a63289080617e841b4d1cf255c739145b4
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Sat Oct 19 08:13:31 2019 -0700
drm/openchrome: Fix for openchrome_gamma_set()
IGA reference was reversed, so this was leading to a freeze.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_crtc.c
b/drivers/gpu/drm/openchrome/openchrome_crtc.c
index 21604c3b99ed..1ad8e050bac9 100644
--- a/drivers/gpu/drm/openchrome/openchrome_crtc.c
+++ b/drivers/gpu/drm/openchrome/openchrome_crtc.c
@@ -62,22 +62,135 @@ static struct vga_regset vpit_table[] = {
{VGA_GFX_I, 0x08, 0xFF, 0xFF }
};
+static void via_iga_common_init(void __iomem *regs)
+{
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /* Be careful with 3C5.15[5] - Wrap Around Disable.
+ * It must be set to 1 for proper operation. */
+ /* 3C5.15[5] - Wrap Around Disable
+ * 0: Disable (For Mode 0-13)
+ * 1: Enable
+ * 3C5.15[1] - Extended Display Mode Enable
+ * 0: Disable
+ * 1: Enable */
+ svga_wseq_mask(regs, 0x15, BIT(5) | BIT(1), BIT(5) | BIT(1));
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_iga1_set_color_depth(
+ struct openchrome_drm_private *dev_private,
+ u8 depth)
+{
+ u8 value;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ value = 0x00;
+
+ /* Set the color depth for IGA1. */
+ switch (depth) {
+ case 8:
+ break;
+ case 16:
+ /* Bit 4 is for 555 (15-bit) / 565 (16-bit) color selection. */
+ value |= BIT(4) | BIT(2);
+ break;
+ case 24:
+ case 32:
+ value |= BIT(3) | BIT(2);
+ break;
+ default:
+ break;
+ }
+
+ if ((depth == 8) || (depth == 16) ||
+ (depth == 24) || (depth == 32)) {
+ /* 3C5.15[4] - Hi Color Mode Select
+ * 0: 555
+ * 1: 565
+ * 3C5.15[3:2] - Display Color Depth Select
+ * 00: 8bpp
+ * 01: 16bpp
+ * 10: 30bpp
+ * 11: 32bpp */
+ svga_wseq_mask(VGABASE, 0x15, value,
+ BIT(4) | BIT(3) | BIT(2));
+ DRM_INFO("IGA1 Color Depth: %d bit\n", depth);
+ } else {
+ DRM_ERROR("Unsupported IGA1 Color Depth: %d bit\n",
+ depth);
+ }
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+static void via_iga2_set_color_depth(
+ struct openchrome_drm_private *dev_private,
+ u8 depth)
+{
+ u8 value;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ value = 0x00;
+
+ /* Set the color depth for IGA2. */
+ switch (depth) {
+ case 8:
+ break;
+ case 16:
+ value = BIT(6);
+ break;
+ case 24:
+ case 32:
+ value = BIT(7) | BIT(6);
+ break;
+ default:
+ break;
+ }
+
+ if ((depth == 8) || (depth == 16) ||
+ (depth == 24) || (depth == 32)) {
+ /* 3X5.67[7:6] - Display Color Depth Select
+ * 00: 8bpp
+ * 01: 16bpp
+ * 10: 30bpp
+ * 11: 32bpp */
+ svga_wcrt_mask(VGABASE, 0x67, value, 0xC0);
+ DRM_INFO("IGA2 Color Depth: %d bit\n", depth);
+ } else {
+ DRM_ERROR("Unsupported IGA2 Color Depth: %d bit\n",
+ depth);
+ }
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
static int openchrome_gamma_set(struct drm_crtc *crtc,
u16 *r, u16 *g, u16 *b,
uint32_t size,
struct drm_modeset_acquire_ctx *ctx)
{
- struct via_crtc *iga = container_of(crtc,
- struct via_crtc, base);
struct openchrome_drm_private *dev_private =
crtc->dev->dev_private;
+ struct via_crtc *iga = container_of(crtc,
+ struct via_crtc, base);
int end = (size > 256) ? 256 : size, i;
- u8 val = 0, sr1a = vga_rseq(VGABASE, 0x1A);
+ u8 val = 0, sr1a;
+ int ret = 0;
- if (!crtc->enabled || !crtc->primary->fb)
- return -EINVAL;
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
- if (iga->index) {
+ sr1a = vga_rseq(VGABASE, 0x1A);
+
+ if ((!crtc->enabled) || (!crtc->primary->fb)) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ if (!iga->index) {
if (crtc->primary->fb->format->cpp[0] * 8 == 8) {
/* Prepare for initialize IGA1's LUT: */
vga_wseq(VGABASE, 0x1A, sr1a & 0xFE);
@@ -200,113 +313,10 @@ static int openchrome_gamma_set(struct drm_crtc *crtc,
vga_wseq(VGABASE, 0x1A, sr1a);
}
}
- return 0;
-}
-
-static void via_iga_common_init(void __iomem *regs)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /* Be careful with 3C5.15[5] - Wrap Around Disable.
- * It must be set to 1 for proper operation. */
- /* 3C5.15[5] - Wrap Around Disable
- * 0: Disable (For Mode 0-13)
- * 1: Enable
- * 3C5.15[1] - Extended Display Mode Enable
- * 0: Disable
- * 1: Enable */
- svga_wseq_mask(regs, 0x15, BIT(5) | BIT(1), BIT(5) | BIT(1));
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
-static void via_iga1_set_color_depth(
- struct openchrome_drm_private *dev_private,
- u8 depth)
-{
- u8 value;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- value = 0x00;
-
- /* Set the color depth for IGA1. */
- switch (depth) {
- case 8:
- break;
- case 16:
- /* Bit 4 is for 555 (15-bit) / 565 (16-bit) color selection. */
- value |= BIT(4) | BIT(2);
- break;
- case 24:
- case 32:
- value |= BIT(3) | BIT(2);
- break;
- default:
- break;
- }
-
- if ((depth == 8) || (depth == 16) ||
- (depth == 24) || (depth == 32)) {
- /* 3C5.15[4] - Hi Color Mode Select
- * 0: 555
- * 1: 565
- * 3C5.15[3:2] - Display Color Depth Select
- * 00: 8bpp
- * 01: 16bpp
- * 10: 30bpp
- * 11: 32bpp */
- svga_wseq_mask(VGABASE, 0x15, value,
- BIT(4) | BIT(3) | BIT(2));
- DRM_INFO("IGA1 Color Depth: %d bit\n", depth);
- } else {
- DRM_ERROR("Unsupported IGA1 Color Depth: %d bit\n",
- depth);
- }
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
-static void via_iga2_set_color_depth(
- struct openchrome_drm_private *dev_private,
- u8 depth)
-{
- u8 value;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- value = 0x00;
-
- /* Set the color depth for IGA2. */
- switch (depth) {
- case 8:
- break;
- case 16:
- value = BIT(6);
- break;
- case 24:
- case 32:
- value = BIT(7) | BIT(6);
- break;
- default:
- break;
- }
-
- if ((depth == 8) || (depth == 16) ||
- (depth == 24) || (depth == 32)) {
- /* 3X5.67[7:6] - Display Color Depth Select
- * 00: 8bpp
- * 01: 16bpp
- * 10: 30bpp
- * 11: 32bpp */
- svga_wcrt_mask(VGABASE, 0x67, value, 0xC0);
- DRM_INFO("IGA2 Color Depth: %d bit\n", depth);
- } else {
- DRM_ERROR("Unsupported IGA2 Color Depth: %d bit\n",
- depth);
- }
+exit:
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
}
static void openchrome_crtc_destroy(struct drm_crtc *crtc)
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