drivers/gpu/drm/via/via_crtc.c |   99 ++++++++++++++++++++---------------------
 drivers/gpu/drm/via/via_drv.h  |   27 -----------
 2 files changed, 52 insertions(+), 74 deletions(-)

New commits:
commit 87476556ecec4c2576762467f48d6ebeca6bcdba
Author: Kevin Brace <kevinbr...@bracecomputerlab.com>
Date:   Wed Feb 1 20:53:07 2023 -0800

    drm/via: Version bumped to 3.6.3
    
    Signed-off-by: Kevin Brace <kevinbr...@bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index d15325d24d5e..2f916891dbd0 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -44,10 +44,10 @@
 
 #define DRIVER_MAJOR           3
 #define DRIVER_MINOR           6
-#define DRIVER_PATCHLEVEL      2
+#define DRIVER_PATCHLEVEL      3
 #define DRIVER_NAME            "via"
 #define DRIVER_DESC            "OpenChrome DRM for VIA Technologies Chrome"
-#define DRIVER_DATE            "20230112"
+#define DRIVER_DATE            "20230201"
 #define DRIVER_AUTHOR          "OpenChrome Project"
 
 
commit 86057a53419e51a3f1688a5fea02cdcfb3a42de9
Author: Kevin Brace <kevinbr...@bracecomputerlab.com>
Date:   Wed Feb 1 20:45:03 2023 -0800

    drm/via: Delete via_lock_crtc()
    
    Signed-off-by: Kevin Brace <kevinbr...@bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index b5e23e9f296e..faaac0566119 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -1730,9 +1730,6 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
                }
        }
 
-       /* Relock */
-       via_lock_crtc(VGABASE);
-
        if (!iga->index) {
                /* Set non-interlace / interlace mode. */
                via_iga1_set_interlace_mode(VGABASE,
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 8002acc08fec..d15325d24d5e 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -30,8 +30,6 @@
 #define _VIA_DRV_H
 
 
-#include <video/vga.h>
-
 #include <drm/drm_connector.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_encoder.h>
@@ -304,13 +302,6 @@ struct via_drm_priv {
 #define VGABASE (VIA_BASE+VIA_MMIO_VGABASE)
 
 
-static inline void
-via_lock_crtc(void __iomem *regs)
-{
-       svga_wcrt_mask(regs, 0x11, BIT(7), BIT(7));
-}
-
-
 extern int via_driver_num_ioctls;
 
 extern struct ttm_device_funcs via_bo_driver;
commit 33c33333b32e4ed3df082acb06df2a1a15fa43dc
Author: Kevin Brace <kevinbr...@bracecomputerlab.com>
Date:   Wed Feb 1 20:44:11 2023 -0800

    drm/via: Delete via_unlock_crtc()
    
    Signed-off-by: Kevin Brace <kevinbr...@bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index 2b37ab23a63f..b5e23e9f296e 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -1601,8 +1601,20 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
        /* Load standard registers */
        via_load_vpit_regs(dev_priv);
 
-       /* Unlock */
-       via_unlock_crtc(VGABASE, pdev->device);
+       /*
+        * For VX855 and VX900 chipsets, CRTC unlock register is
+        * CR47[4].  For all others, CR47[0].
+        */
+       if ((pdev->device == PCI_DEVICE_ID_VIA_CHROME9_HCM) ||
+               (pdev->device == PCI_DEVICE_ID_VIA_CHROME9_HD)) {
+               reg_value = BIT(4);
+       } else {
+               reg_value = BIT(0);
+       }
+
+       /* Unlock CRTC registers. */
+       svga_wcrt_mask(VGABASE, 0x11, 0x00, BIT(7));
+       svga_wcrt_mask(VGABASE, 0x47, 0x00, reg_value);
 
        if (!iga->index) {
                /* IGA1 reset */
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index e753e58a45ed..8002acc08fec 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -30,8 +30,6 @@
 #define _VIA_DRV_H
 
 
-#include <linux/pci_ids.h>
-
 #include <video/vga.h>
 
 #include <drm/drm_connector.h>
@@ -312,18 +310,6 @@ via_lock_crtc(void __iomem *regs)
        svga_wcrt_mask(regs, 0x11, BIT(7), BIT(7));
 }
 
-static inline void
-via_unlock_crtc(void __iomem *regs, int pci_id)
-{
-       u8 mask = BIT(0);
-
-       svga_wcrt_mask(regs, 0x11, 0, BIT(7));
-       if ((pci_id == PCI_DEVICE_ID_VIA_CHROME9_HCM) ||
-           (pci_id == PCI_DEVICE_ID_VIA_CHROME9_HD))
-               mask = BIT(4);
-       svga_wcrt_mask(regs, 0x47, 0, mask);
-}
-
 
 extern int via_driver_num_ioctls;
 
commit f7e25b99f3161b8dbc3e81475bfb99d0ccdbac95
Author: Kevin Brace <kevinbr...@bracecomputerlab.com>
Date:   Tue Jan 17 14:18:46 2023 -0600

    drm/via: Rearrange mode setting code
    
    Signed-off-by: Kevin Brace <kevinbr...@bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index 2d3454f2f3b7..2b37ab23a63f 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -1598,13 +1598,13 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
 
        DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
-       if (!iga->index) {
-               /* Load standard registers */
-               via_load_vpit_regs(dev_priv);
+       /* Load standard registers */
+       via_load_vpit_regs(dev_priv);
 
-               /* Unlock */
-               via_unlock_crtc(VGABASE, pdev->device);
+       /* Unlock */
+       via_unlock_crtc(VGABASE, pdev->device);
 
+       if (!iga->index) {
                /* IGA1 reset */
                vga_wcrt(VGABASE, 0x09, 0x00); /* initial CR09=0 */
                svga_wcrt_mask(VGABASE, 0x11, 0x00, BIT(6));
@@ -1635,48 +1635,7 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
 
                svga_wcrt_mask(VGABASE, 0x47,
                                reg_value, BIT(7) | BIT(6) | BIT(3));
-
-               /* Relock */
-               via_lock_crtc(VGABASE);
-
-               /* Set non-interlace / interlace mode. */
-               via_iga1_set_interlace_mode(VGABASE,
-                                       adjusted_mode->flags &
-                                       DRM_MODE_FLAG_INTERLACE);
-
-               /* No HSYNC shift. */
-               via_iga1_set_hsync_shift(VGABASE, 0x05);
-
-               /* Load display FIFO. */
-               ret = via_iga1_display_fifo_regs(dev, dev_priv,
-                                               iga, adjusted_mode,
-                                               crtc->primary->fb);
-               if (ret) {
-                       goto exit;
-               }
-
-               /* Set PLL */
-               if (adjusted_mode->clock) {
-                       u32 clock = adjusted_mode->clock * 1000;
-                       u32 pll_regs;
-
-                       if (iga->scaling_mode & VIA_SHRINK)
-                               clock *= 2;
-                       pll_regs = via_get_clk_value(crtc->dev, clock);
-                       via_set_vclock(crtc, pll_regs);
-               }
-
-               via_iga_common_init(pdev, VGABASE);
-
-               /* Set palette LUT to 8-bit mode. */
-               via_iga1_set_palette_lut_resolution(VGABASE, true);
        } else {
-               /* Load standard registers */
-               via_load_vpit_regs(dev_priv);
-
-               /* Unlock */
-               via_unlock_crtc(VGABASE, pdev->device);
-
                /* disable IGA scales first */
                via_disable_iga_scaling(crtc);
 
@@ -1757,10 +1716,44 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
                                }
                        }
                }
+       }
+
+       /* Relock */
+       via_lock_crtc(VGABASE);
+
+       if (!iga->index) {
+               /* Set non-interlace / interlace mode. */
+               via_iga1_set_interlace_mode(VGABASE,
+                                       adjusted_mode->flags &
+                                       DRM_MODE_FLAG_INTERLACE);
+
+               /* No HSYNC shift. */
+               via_iga1_set_hsync_shift(VGABASE, 0x05);
+
+               /* Load display FIFO. */
+               ret = via_iga1_display_fifo_regs(dev, dev_priv,
+                                               iga, adjusted_mode,
+                                               crtc->primary->fb);
+               if (ret) {
+                       goto exit;
+               }
+
+               /* Set PLL */
+               if (adjusted_mode->clock) {
+                       u32 clock = adjusted_mode->clock * 1000;
+                       u32 pll_regs;
+
+                       if (iga->scaling_mode & VIA_SHRINK)
+                               clock *= 2;
+                       pll_regs = via_get_clk_value(crtc->dev, clock);
+                       via_set_vclock(crtc, pll_regs);
+               }
 
-               /* Relock */
-               via_lock_crtc(VGABASE);
+               via_iga_common_init(pdev, VGABASE);
 
+               /* Set palette LUT to 8-bit mode. */
+               via_iga1_set_palette_lut_resolution(VGABASE, true);
+       } else {
                /* Set non-interlace / interlace mode. */
                via_iga2_set_interlace_mode(VGABASE,
                                        adjusted_mode->flags &
@@ -1792,7 +1785,6 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
 
                svga_wcrt_mask(VGABASE, 0x6A, BIT(7), BIT(7));
        }
-
 exit:
        DRM_DEBUG_KMS("Exiting %s.\n", __func__);
 }

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