update 2 -sorry for the chatter The logic "explosion" when targeting V5 was cause by a subtle, latent defect in our code that was brought out by ISE 13.4. We have corrected the code in our upstream repo and are working through all regression tests. There should be no FUD surrounding ISE 13.4.
If you are interested; a corrected SRL inference example is checked in here: https://github.com/ShepardSiegel/ocpi/blob/master/libsrc/hdl/ocpi/arSRLFIFOD.v Thanks to Xilinx FAE Jim Wu for his help! http://sites.google.com/site/adepthome/ -Shep On Thu, Jan 19, 2012 at 6:37 PM, Shepard Siegel < [email protected]> wrote: > update - sorry for the chatter > > All of the V6 and K7 builds with 13.4 look fine so far. > We found an issue with V5 targets where XST is not inferring SRLs the way > it used to. > The symptom is register explosion in XST (.srp) and later in MAP (.mrp). > Chasing this issue now - will update when we have new info. > > > > On Thu, Jan 19, 2012 at 4:14 PM, Shepard Siegel < > [email protected]> wrote: > >> Xilinx recently released ISE 13.4 >> We are running regressions now; ml605 golden; working through V5, K7, >> OPED, etc. >> There is no immediate impact on the opencpi.org repo. No immediate >> impact on NetFPGA10G. >> Those cloning from the Atomic Rules upsteam git repo will find the xst >> prim libs now built for 13.4 as in the Readme: >> https://github.com/ShepardSiegel/ocpi/blob/master/README >> (so no other version will work w/o recompile - or direct Verilog >> compilation). >> -Shep >> >> >> -- >> Shepard Siegel, CTO >> atomicrules.com >> blog.atomicrules.com >> >> >
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