riscv port does not exist yet

Signed-off-by: Khem Raj <[email protected]>
---
 meta/recipes-support/libunwind/libunwind_1.5.0.bb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/meta/recipes-support/libunwind/libunwind_1.5.0.bb 
b/meta/recipes-support/libunwind/libunwind_1.5.0.bb
index 089c4064f4..5e4693e205 100644
--- a/meta/recipes-support/libunwind/libunwind_1.5.0.bb
+++ b/meta/recipes-support/libunwind/libunwind_1.5.0.bb
@@ -18,6 +18,9 @@ EXTRA_OECONF_append_libc-musl = " --disable-documentation 
--disable-tests --enab
 ARM_INSTRUCTION_SET_armv4 = "arm"
 ARM_INSTRUCTION_SET_armv5 = "arm"
 
+COMPATIBLE_HOST_riscv64 = "null"
+COMPATIBLE_HOST_riscv32 = "null"
+
 LDFLAGS += "-Wl,-z,relro,-z,now ${@bb.utils.contains('DISTRO_FEATURES', 
'ld-is-gold', ' -fuse-ld=bfd ', '', d)}"
 
 SECURITY_LDFLAGS_append_libc-musl = " -lssp_nonshared"
-- 
2.30.1

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