This is ok with me On Tue, Mar 9, 2021 at 12:14 PM Andrei Gherzan <[email protected]> wrote:
> From: Andrei Gherzan <[email protected]> > > Signed-off-by: Andrei Gherzan <[email protected]> > --- > ...-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch | 185 ++++++++++++++++++ > meta/recipes-core/glibc/glibc_2.33.bb | 1 + > 2 files changed, 186 insertions(+) > create mode 100644 > meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch > > diff --git > a/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch > b/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch > new file mode 100644 > index 0000000000..3a004e227f > --- /dev/null > +++ > b/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch > @@ -0,0 +1,185 @@ > +From 750b00a1ddae220403fd892a6fd4e0791ffd154a Mon Sep 17 00:00:00 2001 > +From: "H.J. Lu" <[email protected]> > +Date: Fri, 18 Sep 2020 07:55:14 -0700 > +Subject: [PATCH] x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] > + > + x86: Move x86 processor cache info to cpu_features > + > +missed _SC_LEVEL1_ICACHE_LINESIZE. > + > +1. Add level1_icache_linesize to struct cpu_features. > +2. Initialize level1_icache_linesize by calling handle_intel, > +handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE. > +3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE. > + > +Upstream-Status: Backport [ > https://sourceware.org/bugzilla/show_bug.cgi?id=27444] > +Signed-off-by: Andrei Gherzan <[email protected]> > +--- > + sysdeps/x86/Makefile | 8 +++ > + sysdeps/x86/cacheinfo.c | 3 + > + sysdeps/x86/dl-cacheinfo.h | 6 ++ > + sysdeps/x86/include/cpu-features.h | 2 + > + .../x86/tst-sysconf-cache-linesize-static.c | 1 + > + sysdeps/x86/tst-sysconf-cache-linesize.c | 57 +++++++++++++++++++ > + 6 files changed, 77 insertions(+) > + create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize-static.c > + create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize.c > + > +diff --git a/sysdeps/x86/Makefile b/sysdeps/x86/Makefile > +index dd82674342..d231263051 100644 > +--- a/sysdeps/x86/Makefile > ++++ b/sysdeps/x86/Makefile > +@@ -208,3 +208,11 @@ $(objpfx)check-cet.out: > $(..)sysdeps/x86/check-cet.awk \ > + generated += check-cet.out > + endif > + endif > ++ > ++ifeq ($(subdir),posix) > ++tests += \ > ++ tst-sysconf-cache-linesize \ > ++ tst-sysconf-cache-linesize-static > ++tests-static += \ > ++ tst-sysconf-cache-linesize-static > ++endif > +diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c > +index 7b8df45e3b..5ea4723ca6 100644 > +--- a/sysdeps/x86/cacheinfo.c > ++++ b/sysdeps/x86/cacheinfo.c > +@@ -32,6 +32,9 @@ __cache_sysconf (int name) > + case _SC_LEVEL1_ICACHE_SIZE: > + return cpu_features->level1_icache_size; > + > ++ case _SC_LEVEL1_ICACHE_LINESIZE: > ++ return cpu_features->level1_icache_linesize; > ++ > + case _SC_LEVEL1_DCACHE_SIZE: > + return cpu_features->level1_dcache_size; > + > +diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > +index a31fa0783a..7cd00b92f1 100644 > +--- a/sysdeps/x86/dl-cacheinfo.h > ++++ b/sysdeps/x86/dl-cacheinfo.h > +@@ -707,6 +707,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > + long int core; > + unsigned int threads = 0; > + unsigned long int level1_icache_size = -1; > ++ unsigned long int level1_icache_linesize = -1; > + unsigned long int level1_dcache_size = -1; > + unsigned long int level1_dcache_assoc = -1; > + unsigned long int level1_dcache_linesize = -1; > +@@ -726,6 +727,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > + > + level1_icache_size > + = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); > ++ level1_icache_linesize > ++ = handle_intel (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features); > + level1_dcache_size = data; > + level1_dcache_assoc > + = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); > +@@ -753,6 +756,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > + shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > + > + level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); > ++ level1_icache_linesize = handle_zhaoxin > (_SC_LEVEL1_ICACHE_LINESIZE); > + level1_dcache_size = data; > + level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); > + level1_dcache_linesize = handle_zhaoxin > (_SC_LEVEL1_DCACHE_LINESIZE); > +@@ -772,6 +776,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); > + > + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); > ++ level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE); > + level1_dcache_size = data; > + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); > + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); > +@@ -833,6 +838,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > + } > + > + cpu_features->level1_icache_size = level1_icache_size; > ++ cpu_features->level1_icache_linesize = level1_icache_linesize; > + cpu_features->level1_dcache_size = level1_dcache_size; > + cpu_features->level1_dcache_assoc = level1_dcache_assoc; > + cpu_features->level1_dcache_linesize = level1_dcache_linesize; > +diff --git a/sysdeps/x86/include/cpu-features.h > b/sysdeps/x86/include/cpu-features.h > +index 624736b40e..39a3f4f311 100644 > +--- a/sysdeps/x86/include/cpu-features.h > ++++ b/sysdeps/x86/include/cpu-features.h > +@@ -874,6 +874,8 @@ struct cpu_features > + unsigned long int rep_stosb_threshold; > + /* _SC_LEVEL1_ICACHE_SIZE. */ > + unsigned long int level1_icache_size; > ++ /* _SC_LEVEL1_ICACHE_LINESIZE. */ > ++ unsigned long int level1_icache_linesize; > + /* _SC_LEVEL1_DCACHE_SIZE. */ > + unsigned long int level1_dcache_size; > + /* _SC_LEVEL1_DCACHE_ASSOC. */ > +diff --git a/sysdeps/x86/tst-sysconf-cache-linesize-static.c > b/sysdeps/x86/tst-sysconf-cache-linesize-static.c > +new file mode 100644 > +index 0000000000..152ae68821 > +--- /dev/null > ++++ b/sysdeps/x86/tst-sysconf-cache-linesize-static.c > +@@ -0,0 +1 @@ > ++#include "tst-sysconf-cache-linesize.c" > +diff --git a/sysdeps/x86/tst-sysconf-cache-linesize.c > b/sysdeps/x86/tst-sysconf-cache-linesize.c > +new file mode 100644 > +index 0000000000..642dbde5d2 > +--- /dev/null > ++++ b/sysdeps/x86/tst-sysconf-cache-linesize.c > +@@ -0,0 +1,57 @@ > ++/* Test system cache line sizes. > ++ Copyright (C) 2021 Free Software Foundation, Inc. > ++ This file is part of the GNU C Library. > ++ > ++ The GNU C Library is free software; you can redistribute it and/or > ++ modify it under the terms of the GNU Lesser General Public > ++ License as published by the Free Software Foundation; either > ++ version 2.1 of the License, or (at your option) any later version. > ++ > ++ The GNU C Library is distributed in the hope that it will be useful, > ++ but WITHOUT ANY WARRANTY; without even the implied warranty of > ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > ++ Lesser General Public License for more details. > ++ > ++ You should have received a copy of the GNU Lesser General Public > ++ License along with the GNU C Library; if not, see > ++ <https://www.gnu.org/licenses/>. */ > ++ > ++#include <stdio.h> > ++#include <stdlib.h> > ++#include <unistd.h> > ++#include <array_length.h> > ++ > ++static struct > ++{ > ++ const char *name; > ++ int _SC_val; > ++} sc_options[] = > ++ { > ++#define N(name) { "_SC_"#name, _SC_##name } > ++ N (LEVEL1_ICACHE_LINESIZE), > ++ N (LEVEL1_DCACHE_LINESIZE), > ++ N (LEVEL2_CACHE_LINESIZE) > ++ }; > ++ > ++static int > ++do_test (void) > ++{ > ++ int result = EXIT_SUCCESS; > ++ > ++ for (int i = 0; i < array_length (sc_options); ++i) > ++ { > ++ long int scret = sysconf (sc_options[i]._SC_val); > ++ if (scret < 0) > ++ { > ++ printf ("sysconf (%s) returned < 0 (%ld)\n", > ++ sc_options[i].name, scret); > ++ result = EXIT_FAILURE; > ++ } > ++ else > ++ printf ("sysconf (%s): %ld\n", sc_options[i].name, scret); > ++ } > ++ > ++ return result; > ++} > ++ > ++#include <support/test-driver.c> > diff --git a/meta/recipes-core/glibc/glibc_2.33.bb > b/meta/recipes-core/glibc/glibc_2.33.bb > index c47826a51e..ac73bbeb7f 100644 > --- a/meta/recipes-core/glibc/glibc_2.33.bb > +++ b/meta/recipes-core/glibc/glibc_2.33.bb > @@ -45,6 +45,7 @@ SRC_URI = > "${GLIBC_GIT_URI};branch=${SRCBRANCH};name=glibc \ > file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch > \ > > file://0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch \ > file://0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch > \ > + > file://0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch \ > " > S = "${WORKDIR}/git" > B = "${WORKDIR}/build-${TARGET_SYS}" > -- > 2.30.1 > > > > >
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