This fixes a build issue that started with 3.1 upgrade
Fixes
| ../ruby-3.1.0/vm_dump.c:916:38: error: use of undeclared identifier 'REG_S1'
|         dump_machine_register(mctx->__gregs[REG_S1], "s1");

Signed-off-by: Khem Raj <raj.k...@gmail.com>
---
 ...ine-REG_S1-and-REG_S2-for-musl-riscv.patch | 30 +++++++++++++++++++
 meta/recipes-devtools/ruby/ruby_3.1.0.bb      |  9 +-----
 2 files changed, 31 insertions(+), 8 deletions(-)
 create mode 100644 
meta/recipes-devtools/ruby/ruby/0001-vm_dump.c-Define-REG_S1-and-REG_S2-for-musl-riscv.patch

diff --git 
a/meta/recipes-devtools/ruby/ruby/0001-vm_dump.c-Define-REG_S1-and-REG_S2-for-musl-riscv.patch
 
b/meta/recipes-devtools/ruby/ruby/0001-vm_dump.c-Define-REG_S1-and-REG_S2-for-musl-riscv.patch
new file mode 100644
index 00000000000..8821325c0fe
--- /dev/null
+++ 
b/meta/recipes-devtools/ruby/ruby/0001-vm_dump.c-Define-REG_S1-and-REG_S2-for-musl-riscv.patch
@@ -0,0 +1,30 @@
+From dfb22e4d6662bf72879eda806eaa78c7b52b519e Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.k...@gmail.com>
+Date: Tue, 25 Jan 2022 20:29:14 -0800
+Subject: [PATCH] vm_dump.c: Define REG_S1 and REG_S2 for musl/riscv
+
+Upstream-Status: Inappropriate [musl bug]
+Signed-off-by: Khem Raj <raj.k...@gmail.com>
+---
+ vm_dump.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/vm_dump.c b/vm_dump.c
+index a98f5aa..957b785 100644
+--- a/vm_dump.c
++++ b/vm_dump.c
+@@ -39,6 +39,11 @@
+ 
+ #define MAX_POSBUF 128
+ 
++#if defined(__riscv) && !defined(__GLIBC__)
++# define REG_S1 9
++# define REG_S2 18
++#endif
++
+ #define VM_CFP_CNT(ec, cfp) \
+   ((rb_control_frame_t *)((ec)->vm_stack + (ec)->vm_stack_size) - \
+    (rb_control_frame_t *)(cfp))
+-- 
+2.35.0
+
diff --git a/meta/recipes-devtools/ruby/ruby_3.1.0.bb 
b/meta/recipes-devtools/ruby/ruby_3.1.0.bb
index e250164d2c4..7a04a364326 100644
--- a/meta/recipes-devtools/ruby/ruby_3.1.0.bb
+++ b/meta/recipes-devtools/ruby/ruby_3.1.0.bb
@@ -11,6 +11,7 @@ SRC_URI += " \
            
file://0004-lib-mkmf.rb-sort-list-of-object-files-in-generated-M.patch \
            
file://0005-Mark-Gemspec-reproducible-change-fixing-784225-too.patch \
            file://0006-Make-gemspecs-reproducible.patch \
+           file://0001-vm_dump.c-Define-REG_S1-and-REG_S2-for-musl-riscv.patch 
\
            "
 
 SRC_URI[sha256sum] = 
"50a0504c6edcb4d61ce6b8cfdbddaa95707195fab0ecd7b5e92654b2a9412854"
@@ -36,18 +37,10 @@ EXTRA_OECONF = "\
 "
 
 EXTRA_OECONF:append:libc-musl = "\
-    LIBS='-lucontext' \
     ac_cv_func_isnan=yes \
     ac_cv_func_isinf=yes \
 "
 
-EXTRA_OECONF:append:libc-musl:riscv64 = "\
-    --with-coroutine=copy \
-"
-EXTRA_OECONF:append:libc-musl:riscv32 = "\
-    --with-coroutine=copy \
-"
-
 PARALLEL_MAKEINST = ""
 
 do_install:append:class-target () {
-- 
2.35.0

-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#160956): 
https://lists.openembedded.org/g/openembedded-core/message/160956
Mute This Topic: https://lists.openembedded.org/mt/88690372/21656
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Reply via email to