On 4/14/22 00:32, Alistair Francis wrote:
On Thu, Apr 14, 2022 at 12:52 PM Khem Raj <[email protected]> wrote:
Signed-off-by: Khem Raj <[email protected]>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 2 ++
meta/conf/machine/include/riscv/tune-riscv.inc | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
b/meta/conf/machine/include/riscv/arch-riscv.inc
index e5611a12a66..230a266563a 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -7,6 +7,8 @@ TUNE_PKGARCH = "${TUNE_PKGARCH:tune-${DEFAULTTUNE}}"
TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', '
-mabi=lp64', ' ', d)}"
TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', '
-mabi=ilp32', ' ', d)}"
+TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nc', '
-march=rv64imafd', ' ', d)}"
I thought Linux expected compressed instruction support, is there
actual hardware that doesn't have compressed instructions?
CDAC in India is designing bunch of cores without C instruction support.
Alistair
+
# Fix: ld: unrecognized option '--hash-style=sysv'
LINKER_HASH_STYLE:libc-newlib = ""
# Fix: ld: unrecognized option '--hash-style=gnu'
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
b/meta/conf/machine/include/riscv/tune-riscv.inc
index cc2896f277b..659801496c9 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -6,6 +6,8 @@ TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
+TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed
instructions"
+
TUNEVALID[bigendian] = "Big endian mode"
AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
@@ -31,3 +33,9 @@ TUNE_FEATURES:tune-riscv32nf = "${TUNE_FEATURES:tune-riscv32}
riscv32nf"
TUNE_ARCH:tune-riscv32nf = "riscv32"
TUNE_PKGARCH:tune-riscv32nf = "riscv32nf"
PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "riscv32nf"
+
+# no compressed
+TUNE_FEATURES:tune-riscv64nc = "${TUNE_FEATURES:tune-riscv64} riscv64nc"
+TUNE_ARCH:tune-riscv64nc = "riscv64"
+TUNE_PKGARCH:tune-riscv64nc = "riscv64nc"
+PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "riscv64nc"
--
2.35.2
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