This was missed when riscv64nc was added Signed-off-by: Khem Raj <raj.k...@gmail.com> --- meta/conf/machine/include/riscv/tune-riscv.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 659801496c..804712077e 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -10,7 +10,7 @@ TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed in TUNEVALID[bigendian] = "Big endian mode" -AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf" +AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # Default TUNE_FEATURES:tune-riscv64 = "riscv64" -- 2.39.2
-=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#177624): https://lists.openembedded.org/g/openembedded-core/message/177624 Mute This Topic: https://lists.openembedded.org/mt/97190843/21656 Group Owner: openembedded-core+ow...@lists.openembedded.org Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-