From: Jialing Zhang <[email protected]>
Signed-off-by: Jialing Zhang <[email protected]>
Signed-off-by: Qizheng Zhu <[email protected]>
---
meta/classes-recipe/libc-package.bbclass | 3 ++-
meta/classes-recipe/meson-routines.bbclass | 2 ++
meta/classes-recipe/rust-target-config.bbclass | 11 +++++++++++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/meta/classes-recipe/libc-package.bbclass
b/meta/classes-recipe/libc-package.bbclass
index 8a99f73ae7..bf160b115d 100644
--- a/meta/classes-recipe/libc-package.bbclass
+++ b/meta/classes-recipe/libc-package.bbclass
@@ -268,7 +268,8 @@ python package_do_split_gconvs () {
"riscv32": " --uint32-align=4 --little-endian ", \
"i586": " --uint32-align=4 --little-endian ", \
"i686": " --uint32-align=4 --little-endian ", \
- "x86_64": " --uint32-align=4 --little-endian " }
+ "x86_64": " --uint32-align=4 --little-endian ", \
+ "loongarch64": " --uint32-align=4 --little-endian " }
if target_arch in locale_arch_options:
localedef_opts = locale_arch_options[target_arch]
diff --git a/meta/classes-recipe/meson-routines.bbclass
b/meta/classes-recipe/meson-routines.bbclass
index 6086fce9d9..a944a8fff1 100644
--- a/meta/classes-recipe/meson-routines.bbclass
+++ b/meta/classes-recipe/meson-routines.bbclass
@@ -23,6 +23,8 @@ def meson_cpu_family(var, d):
return 'arm'
elif arch == 'aarch64_be':
return 'aarch64'
+ elif arch == 'loongarch64':
+ return 'loongarch64'
elif arch == 'mipsel':
return 'mips'
elif arch == 'mips64el':
diff --git a/meta/classes-recipe/rust-target-config.bbclass
b/meta/classes-recipe/rust-target-config.bbclass
index 5e71546fee..21a56ede3e 100644
--- a/meta/classes-recipe/rust-target-config.bbclass
+++ b/meta/classes-recipe/rust-target-config.bbclass
@@ -245,6 +245,14 @@ TARGET_POINTER_WIDTH[riscv64gc] = "64"
TARGET_C_INT_WIDTH[riscv64gc] = "64"
MAX_ATOMIC_WIDTH[riscv64gc] = "64"
+## loongarch64-unknown-linux-{gnu, musl}
+DATA_LAYOUT[loongarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+TARGET_ENDIAN[loongarch64] = "little"
+TARGET_POINTER_WIDTH[loongarch64] = "64"
+TARGET_C_INT_WIDTH[loongarch64] = "32"
+MAX_ATOMIC_WIDTH[loongarch64] = "64"
+FEATURES[loongarch64] = "+d"
+
# Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
# rust's internals won't choke on.
def arch_to_rust_target_arch(arch):
@@ -288,6 +296,7 @@ def llvm_cpu(d):
trans['mips64el'] = "mips64"
trans['riscv64'] = "generic-rv64"
trans['riscv32'] = "generic-rv32"
+ trans['loongarch64'] = "la464"
if target in ["mips", "mipsel", "powerpc"]:
feat = frozenset(d.getVar('TUNE_FEATURES').split())
@@ -367,6 +376,8 @@ def rust_gen_target(d, thing, wd, arch):
tspec['llvm-abiname'] = "lp64d"
if "riscv32" in tspec['llvm-target']:
tspec['llvm-abiname'] = "ilp32d"
+ if "loongarch64" in tspec['llvm-target']:
+ tspec['llvm-abiname'] = "lp64d"
tspec['vendor'] = "unknown"
tspec['target-family'] = "unix"
tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)
--
2.34.1
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