Cortex-A32 is an AArch32-only ARMv8-A core, but its tune was configured as if it were a plain 64-bit-style tune: TUNE_FEATURES lacked both 'arm' and 'thumb', so userspace and the kernel were built as fixed-width ARM rather than Thumb-2, and the package architecture names did not match a Thumb-2 build.
Add 'thumb' so the core is built as Thumb-2, and 'arm' so that feature-arm-thumb.inc honours a recipe's explicit ARM_INSTRUCTION_SET = "arm" instead of silently forcing it to thumb. Without 'arm', ARM_M_OPT is pinned to "thumb" and recipes that request ARM warn, e.g.: Recipe 'libmad' selects ARM_INSTRUCTION_SET to be 'arm', but tune configuration overrides it to 'thumb' On AArch32 the ARMv8 crypto extensions (AES/SHA) are part of the FPU, not just the -march ISA. The 'crypto' feature only appends '+crypto' to -march and leaves -mfpu at plain 'neon', so building the AES intrinsics (e.g. mbedtls aesce.c) fails: error: inlining failed in call to 'always_inline' 'vaesdq_u8': target specific option mismatch Select the crypto FPU by appending crypto-neon-fp-armv8 as the last word of TUNE_CCARGS_MFPU when both 'crypto' and 'neon' are active, mirroring the vfpv4+neon -> neon-vfpv4 idiom in feature-arm-neon.inc. Update PACKAGE_EXTRA_ARCHS to match the resulting package arches: cortexa32hf-neon becomes cortexa32t2hf-neon, and the crypto variant becomes cortexa32t2hf-neon plus cortexa32t2hf-crypto-neon-fp-armv8. AI-Generated: Claude Code (Claude Opus 4.8) Signed-off-by: Alex Kiernan <[email protected]> Signed-off-by: Alex Kiernan <[email protected]> --- meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc b/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc index 0eb938a2403a..f8f876813302 100644 --- a/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc +++ b/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc @@ -5,14 +5,22 @@ TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa32', ' -mcpu=corte require conf/machine/include/arm/arch-armv8a.inc +# On AArch32 the ARMv8 crypto extensions (AES/SHA) live in the FPU, not just +# -march. OE-Core's 'crypto' feature only adds '+crypto' to -march, leaving the +# FPU at plain 'neon', so GCC refuses to inline the AES intrinsics used by e.g. +# mbedtls' aesce.c ("target specific option mismatch"). Select the crypto FPU by +# making it the last word of TUNE_CCARGS_MFPU - the same idiom OE-Core uses for +# the vfpv4+neon -> neon-vfpv4 combination in feature-arm-neon.inc. +TUNE_CCARGS_MFPU .= "${@bb.utils.contains('TUNE_FEATURES', [ 'crypto', 'neon' ], ' crypto-neon-fp-armv8', '', d)}" + # Little Endian base configs AVAILTUNES += "cortexa32 cortexa32-crypto" ARMPKGARCH:tune-cortexa32 = "cortexa32" ARMPKGARCH:tune-cortexa32-crypto = "cortexa32" # We do not want -march since -mcpu is added above to cover for it -TUNE_FEATURES:tune-cortexa32 = "armv8a cortexa32 crc callconvention-hard neon" +TUNE_FEATURES:tune-cortexa32 = "arm armv8a cortexa32 crc callconvention-hard neon thumb" TUNE_FEATURES:tune-cortexa32-crypto = "${TUNE_FEATURES:tune-cortexa32} crypto" -PACKAGE_EXTRA_ARCHS:tune-cortexa32 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa32 cortexa32hf-neon" -PACKAGE_EXTRA_ARCHS:tune-cortexa32-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cortexa32 cortexa32hf-neon cortexa32hf-neon-crypto" +PACKAGE_EXTRA_ARCHS:tune-cortexa32 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa32 cortexa32t2hf-neon" +PACKAGE_EXTRA_ARCHS:tune-cortexa32-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cortexa32 cortexa32t2hf-neon cortexa32t2hf-crypto-neon-fp-armv8" BASE_LIB:tune-cortexa32 = "lib" BASE_LIB:tune-cortexa32-crypto = "lib" -- 2.43.0
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