On Sat, 2026-07-18 at 10:52 +0200, Yoann Congal via lists.openembedded.org wrote: > From: Gustavo Henrique Nihei <[email protected]> > > SRC_URI_RISCV clears every RISC-V ISA extension via > u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per > TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even > though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in > the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default > rv64gc/rv32gc tunes), compressed instructions stay disabled after the > clear fragment runs, and .config ends up with: > > # CONFIG_RISCV_ISA_C is not set > > Building without RVC noticeably inflates .text: on qemuriscv64 > (tune-riscv64, rv64gc), the resulting u-boot binary is 1312625 bytes of > .text without the fix vs 1082853 bytes with CONFIG_RISCV_ISA_C=y > correctly set, 229772 bytes (17.5%) smaller. On size-constrained > RISC-V SPL targets this .text growth can make the SPL .bss VMA overlap > the .text VMA and fail the link. > > Add the missing "c" mapping line, mirroring the existing per-extension > entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV. > > Tested on oe-core master, MACHINE=qemuriscv64, via the > oe-nodistro-master bitbake-setup config: > > bitbake -c cleansstate u-boot && bitbake u-boot > grep CONFIG_RISCV_ISA_C .../u-boot/2026.04/build/.config > # before: "# CONFIG_RISCV_ISA_C is not set" > # after: "CONFIG_RISCV_ISA_C=y" > > do_package_qa passes both before and after; only the ISA config and > resulting .text size change. > > Fixes: cd9e7304481b ("u-boot: Overhaul UBOOT_CONFIG flow")
Should this have been de890297b392 ("u-boot: Dynamic RISC-V ISA
configuration")?
Best regards,
--
Paul Barker
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