On Fri, Oct 4 2024 at 12:45:16 AM -07:00:00, Khem Raj <[email protected]> wrote:
Thanks for following this through. I wonder if we should take the
patch from - <https://github.com/WebKit/WebKit/pull/8696>

I think I already added this patch once. It has been removed once the issue was fixed upstream. There have been lots of changes to the wasm tier since then, so it would probably not work exactly the same way it did, but I haven't even tried so far because that was not the only issue.

Fixed the typo:
diff --git a/Source/JavaScriptCore/jit/GPRInfo.h b/Source/JavaScriptCore/jit/GPRInfo.h
index a4801ba44528..1497058bd8c6 100644
--- a/Source/JavaScriptCore/jit/GPRInfo.h
+++ b/Source/JavaScriptCore/jit/GPRInfo.h
@@ -756,16 +756,16 @@ public:
    static constexpr GPRReg wasmBaseMemoryPointer = regCS3;
    static constexpr GPRReg wasmBoundsCheckingSizeRegister = regCS4;

- static constexpr GPRReg regWS0 = RICSV64Registers::x6;
- static constexpr GPRReg regWS1 = RICSV64Registers::x7;
- static constexpr GPRReg regWA0 = RICSV64Registers::x10;
- static constexpr GPRReg regWA1 = RICSV64Registers::x11;
- static constexpr GPRReg regWA2 = RICSV64Registers::x12;
- static constexpr GPRReg regWA3 = RICSV64Registers::x13;
- static constexpr GPRReg regWA4 = RICSV64Registers::x14;
- static constexpr GPRReg regWA5 = RICSV64Registers::x15;
- static constexpr GPRReg regWA6 = RICSV64Registers::x16;
- static constexpr GPRReg regWA7 = RICSV64Registers::x17;
+ static constexpr GPRReg regWS0 = RISCV64Registers::x6;
+ static constexpr GPRReg regWS1 = RISCV64Registers::x7;
+ static constexpr GPRReg regWA0 = RISCV64Registers::x10;
+ static constexpr GPRReg regWA1 = RISCV64Registers::x11;
+ static constexpr GPRReg regWA2 = RISCV64Registers::x12;
+ static constexpr GPRReg regWA3 = RISCV64Registers::x13;
+ static constexpr GPRReg regWA4 = RISCV64Registers::x14;
+ static constexpr GPRReg regWA5 = RISCV64Registers::x15;
+ static constexpr GPRReg regWA6 = RISCV64Registers::x16;
+ static constexpr GPRReg regWA7 = RISCV64Registers::x17;

static constexpr GPRReg patchpointScratchRegister = RISCV64Registers::x30; // Should match dataTempRegister

--

And to prevent failure in automated code generation I also, in lack of knowledge, added a fantasy value here:

diff --git a/Source/JavaScriptCore/llint/LowLevelInterpreter.cpp b/Source/JavaScriptCore/llint/LowLevelInterpreter.cpp
index 76c46889c329..4888a753e1d4 100644
--- a/Source/JavaScriptCore/llint/LowLevelInterpreter.cpp
+++ b/Source/JavaScriptCore/llint/LowLevelInterpreter.cpp
@@ -584,6 +584,9 @@ JSValue CLoop::execute(OpcodeID entryOpcodeID, void* executableAddress, VM* vm, #define OFFLINE_ASM_ALIGN_TRAP(align) OFFLINE_ASM_BEGIN_SPACER "\n .balign " #align ", 0xcc\n" // pad with int 3 instructions
#elif CPU(ARM)
#define OFFLINE_ASM_ALIGN_TRAP(align) OFFLINE_ASM_BEGIN_SPACER "\n .balignw " #align ", 0xde00\n" // pad with udf instructions
+#elif CPU(RISCV64)
+#define OFFLINE_ASM_ALIGN_TRAP(align) OFFLINE_ASM_BEGIN_SPACER "\n .balignw " #align ", 0x00\n" // pad with instructions
+
#endif

#define OFFLINE_ASM_EXPORT_SYMBOL(symbol)
--

That helped to compile the LowLevelInterpreter, but I didn't look any further because I felt I lacked too much knowledge at the moment to continue.


-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#112657): 
https://lists.openembedded.org/g/openembedded-devel/message/112657
Mute This Topic: https://lists.openembedded.org/mt/108526034/21656
Group Owner: [email protected]
Unsubscribe: https://lists.openembedded.org/g/openembedded-devel/unsub 
[[email protected]]
-=-=-=-=-=-=-=-=-=-=-=-

Reply via email to