Roland Dreier <[EMAIL PROTECTED]> writes: > Eric> Given that hypertransport interrupts are simply encoded as > Eric> posted write packets it may be possible to send an > Eric> appropriate interrupt even without explicit bridge support. > > I would be quite surprised if you could generate a PCI write cycle > that gets turned into an HT interrupt message without the bridge > supporting MSI. It seems to me that any write cycle is either going > to get turned into an upstream HT write if it is to a valid address, > or get dropped or hose the system if it's to an invalid address.
A HT interrupt message is a write cycle to a an address in the range 0xFDF8000000 - 0xFDF8FFFFFF. So a PCI write cycle getting turned into a HT write cycle is useful behavior. The question is can we generate an appropriate write to those addresses from the card, and will the 8131 filter a write to those addresses. Section J on page 283 of the HT 2.0a specification has a good reference as to the allocation of the HT address space. HT only has memory read/write cycles. Everything else is mapped to memory read/write cycles at a reserved address. Usually in the last 12GB before 1TB. Eric _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
