On Wed, May 18, 2005 at 08:00:15PM -0700, Felix Marti wrote: > Hi Roland, > > define SMP :)
Anytime a CPU is cache coherent with another CPU. > at these rates, system architecture comes into place, Definitely. The architecture puts boundaries on how coherency can be implemented...and thus available memory bus bandwidth. grant _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
