On Thu, Jun 23, 2005 at 07:45:55PM +0300, Michael S. Tsirkin wrote: > It seems that compiler generates a single instruction for this shift.
If so, then gcc or the code gen backend should generate a warning about overflowing the encoding. This sounds like a toolchain bug. > And CPU designers apparently have cut a corner by simply using only low 6 bits > in the operand of a shift, so that 1ull<<64 is same as 1ull<<(64&0x37), or 1. It might be the instruction encoding is the limiting factor and not the CPU implementation. I don't have my dead-tree IA32 arch books to look up the encoding. Ie gcc might need to learn a new instruction for 64-bit platforms. I've run into this on the parisc support in the gnu tool chain. grant _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
