> +#define clear_cacheline(adr) __asm__ __volatile("dcbz 0,%0"::"r"(adr))Have you quantified how much of a win using dcbz is for you? If it is a sufficient win to be worth using, I still think this is really the wrong abstraction, because it requires the driver code that uses clear_cacheline() to know that cachelines are 32 bytes. Something like clear_range() would be better, where the cacheline size is encapsulated within the implementation. - R. _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
