I must have had an aneurysm, there are a bunch of these things. I'll fix and repost.
On Thu, 2006-03-16 at 18:17 -0600, Tom Tucker wrote: > On Thu, 2006-03-16 at 14:50 -0800, Roland Dreier wrote: > > > - BE issue resolved by using __raw_write[lw](cpu_to_be[32|16]... > > > > I think maybe you sent out the wrong patchset (or maybe I screwed up > > my mail folder and have an old patchset). But I see stuff like: > > > > > +#define C2_SET_CUR_RX(c2dev, cur_rx) \ > > > + writel(cpu_to_be32(cur_rx), c2dev->mmio_txp_ring + 4092) > > > This looks like an oversight... > > > which is going to be bad on a big-endian arch. > > But there are other writel's in the code that I thought were correct. > For example, if the byte ordering was excpected to be PCI/LE: > - write[wl](0,...) benign, but arguably bogus > - write[wl](LE anything, ...) should be correct, yes? > - write[wl](cpu_xxx, ... ) any that remain are oversights. > > > > > BTW, I'm setting up my PPC 4xx board again soon, so I'll be able to > > try this driver on a big-endian, non-cache-coherent DMA system. > > - R. > > _______________________________________________ > openib-general mailing list > [email protected] > http://openib.org/mailman/listinfo/openib-general > > To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
