> struct ipoib_rx_buf *rx_ring ____cacheline_aligned_in_smp; > struct ib_wc recv_ibwc[IPOIB_NUM_RECV_WC]; > > spinlock_t tx_lock; ____cacheline_aligned_in_smp; > struct ipoib_tx_buf *tx_ring; > unsigned tx_head; > unsigned tx_tail; > struct ib_sge tx_sge; > struct ib_send_wr tx_wr; > struct ib_wc ibwc[IPOIB_NUM_WC];
Yes, that looks like the best thing to me. You have no false sharing between RX and TX, and things are laid out as compactly as possible. - R. _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
