> I just took a quick look at asm-ia64/io.h and there is __ia64_mf_a > barriers after all non-posted IO operations (ib/outb). config write and > config read transcations have identical rules to IO transactions at > the PCI bus level. > > I'm going to go out on a limb here and say that if Linux code assumes > strong ordering of IO operations then it makes sense to also assume > strong ordering on config writes. So, instead of patching mthca with > this barrier it should go in the Altix config access mechanism..
I don't really know what mf.a does on ia64, but it seems likely that even if the CPU issues and retires the reads and writes in order (which is all a CPU barrier is likely to do), we would still have a problem where the PCI-X host bridge allows the MMIO read to pass the config write, because the config write is still pending a split completion on the bus. And a quick web search finds "interesting" stuff like this: > Platform-acceptance is a tricky business, as it's, well, platform > dependent (note that "mf.a" doesn't really guarantee to do anything). So I'm inclined to think this patch is correct. However, I'll check with linux-pci and linux-ia64 before asking Linus to merge it. Thanks, Roland _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
