> > > + /* CPU writes to non-reserved MTTs, while HCA might DMA to > > reserved mtts */ > > > + mdev->limits.reserved_mtts = max(dma_get_cache_alignment() / > > (int)sizeof(u64), > > > + mdev->limits.reserved_mtts); > > > > I don't follow this -- first of all, what guarantee is there that the > > reserved MTTs end on a cacheline boundary just because they take up > > more than a single cacheline? It seems this should really be using > > ALIGN() somehow. > > Actually, I think that we really must have each of the tables start at > ICM-page aligned addresses. I think this happened to work fine so far > as profile was hard-coded, but with new module option code > this might not be the case anymore. > > Since we access some of them from CPU and some from hardware, we really need > them different tables separate dma cache lines too. ICM-page alignment > probably > gives this to us for free, but the following patch makes this assumption > explicit. > > Pls review. > > Warning: untested patch. > > Signed-off-by: Michael S. Tsirkin <[EMAIL PROTECTED]>
I see now this is broken. Working on an updated patch. -- MST _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
