On 10/19/19 09:21 PM, Carl Brewer wrote:
On 20/10/2019 5:08 am, Michal Nowak wrote:
Those two failing services are from the
system/virtualbox/virtualbox-additions package which is meant to be
installed only on VirtualBox guest. Since this is a physical machine
(right?), remove it please, restart and retry the VM start.
Done, and yes, this is the physical machine that is the host.
Now the kernel module not showing up warning has gone away, but it still
crashes the server when I start a guest VM.
If it crashes, can you gather more information from the crash dump? How
to do it is described here:
https://illumos.org/docs/user-guide/debug-systems/#gathering-information-from-a-crash-dump.
It could be the same thing Geoff reported recently...
Michal
I'm away for two days as of today, will resume working on this when I
get back. Thank you for your help, Michal.
Please, install diagnostic/cpuid package and attach output of `cpuid`
as a file.
CPU 0:
Maximum basic CPUID leaf: 0x00000016
CPU vendor string: 'GenuineIntel'
Signature: 0x000906ea
Family: 0x06 (6)
Model: 0x9e (158)
Stepping: 0x0a (10)
Local APIC: 0
Maximum number of APIC IDs per package: 16
CLFLUSH size: 64
Brand ID: 0
Base features, edx:
x87 FPU on chip
virtual-8086 mode enhancement
debugging extensions
page size extensions
time stamp counter
RDMSR and WRMSR support
physical address extensions
machine check exception
CMPXCHG8B instruction
APIC on chip
SYSENTER and SYSEXIT instructions
memory type range registers
PTE global bit
machine check architecture
conditional move instruction
page attribute table
36-bit page size extension
CLFLUSH instruction
debug store
ACPI
MMX instruction set
FXSAVE/FXRSTOR instructions
SSE instructions
SSE2 instructions
self snoop
max APIC IDs reserved field is valid
thermal monitor
pending break enable
Base features, ecx:
SSE3 instructions
PCLMULQDQ instruction
64-bit DS area
MONITOR/MWAIT instructions
CPL qualified debug store
virtual machine extensions
Enhanced Intel SpeedStep
thermal monitor 2
SSSE3 instructions
silicon debug
fused multiply-add AVX instructions
CMPXCHG16B instruction
xTPR update control
perfmon and debug capability
process-context identifiers
SSE4.1 instructions
SSE4.2 instructions
x2APIC
MOVBE instruction
POPCNT instruction
TSC deadline
AES instructions
XSAVE/XRSTOR instructions
OS-enabled XSAVE/XRSTOR
AVX instructions
16-bit FP conversion instructions
RDRAND instruction
Cache descriptors:
[NOTICE] For cache data, see Deterministic Cache Parameters leaf
instead
Code TLB: 2MB or 4MB pages
fully associative
8 entries
Write-back invalidates lower level caches
Code TLB: 4KB pages
8-way set associative
128 entries
Write-back invalidates lower level caches
Data TLB: 1GB pages
4-way set associative
4 entries
Write-back invalidates lower level caches
Undocumented descriptor
Data TLB: 2MB or 4MB pages
4-way set associative
32 entries
Write-back invalidates lower level caches
Undocumented descriptor
Data TLB: 4KB pages
4-way set associative
64 entries
Write-back invalidates lower level caches
Shared TLB: 1GB pages
4-way set associative
16 entries
Write-back invalidates lower level caches
Undocumented descriptor
Shared TLB: 4KB or 2MB pages
4-way set associative
1536 entries
Write-back invalidates lower level caches
Undocumented descriptor
64-byte prefetching
Processor serial number: disabled (or not supported)
Deterministic Cache Parameters:
32KB L1 data cache
8-way set associative
64 byte line size
Self-initializing
Write-back invalidates lower level caches
Shared by max 2 threads
32KB L1 code cache
8-way set associative
64 byte line size
Self-initializing
Write-back invalidates lower level caches
Shared by max 2 threads
256KB L2 unified cache
4-way set associative
64 byte line size
Self-initializing
Write-back invalidates lower level caches
Shared by max 2 threads
9MB L3 unified cache
12-way set associative
64 byte line size
Self-initializing
Inclusive of lower cache levels
Complex indexing
Write-back invalidates lower level caches
Shared by max 16 threads
MONITOR/MWAIT features:
Smallest monitor-line size: 64 bytes
Largest monitor-line size: 64 bytes
Interrupts as break-event for MWAIT, even when interrupts off
C1 sub C-states supported by MWAIT: 2
C2 sub C-states supported by MWAIT: 1
C3 sub C-states supported by MWAIT: 2
C4 sub C-states supported by MWAIT: 4
Intel Thermal and Power Management Features:
Digital temperature sensor
Intel Turbo Boost Technology
Always running APIC timer (ARAT)
Power limit notification controls
Clock modulation duty cycle extensions
Package thermal management
Hardware-managed P-state base support (HWP)
HWP notification interrupt enable MSR
HWP activity window MSR
HWP energy/performance preference MSR
Hardware duty cycle programming (HDC)
Hardware Coordination Feedback Capability (APERF and MPERF)
Interrupt thresholds in DTS: 2
Structured extended feature flags (ecx=0), ebx:
FSGSBASE instructions
IA32_TSC_ADJUST MSR supported
Software Guard Extensions (SGX)
Bit Manipulation Instructions (BMI1)
Advanced Vector Extensions 2.0 (AVX2)
Supervisor Mode Execution Protection (SMEP)
Bit Manipulation Instructions 2 (BMI2)
Enhanced REP MOVSB/STOSB
INVPCID instruction
x87 FPU CS and DS deprecated
Memory Protection Extensions (MPX)
RDSEED instruction
Multi-Precision Add-Carry Instruction Extensions (ADX)
Supervisor Mode Access Prevention (SMAP)
CLFLUSHOPT instruction
Intel Processor Trace
Structured extended feature flags (ecx=0), ecx:
SGX_LC (SGX Launch Configuration)
Architectural Performance Monitoring
Version: 4
Counters per logical processor: 8
Counter bit width: 48
Number of fixed-function counters: 3
Bit width of fixed-function counters: 48
Supported performance counters:
Core cycles
Instructions retired
Reference cycles
Last-level cache reference
Last-level cache miss
Branches retired
Branches mispredicted
x2APIC Processor Topology:
Inferred information:
Logical total: 6
Logical per socket: 6
Cores per socket: 6
Threads per core: 1
x2APIC ID 0 (socket 0, core 0, thread 0)
Extended State Enumeration
Valid bit fields for lower 32 bits of XCR0:
0 - Legacy x87
1 - 128-bit SSE
2 - 256-bit AVX YMM_Hi128
3 - MPX bound registers
4 - MPX bound configuration
Valid bit fields for upper 32-bits of XCR0:
0x00000000
Maximum size required for all enabled features: 832 bytes
Maximum size required for all supported features: 1088 bytes
Features available:
0 - XSAVEOPT
1 - XSAVEC and compacted XRSTOR
2 - XGETBV with ECX=1
3 - XSAVES/XRSTORS and IA32_XSS
Extended state for 256-bit AVX YMM_Hi128 requires 256 bytes, offset 576
Extended state for MPX bound registers requires 64 bytes, offset 960
Extended state for MPX bound configuration requires 64 bytes, offset
1024
Processor Trace Enumeration
CR3 filtering
Configurable PSB, Cycle-Accurate Mode
Filtering preserved across warm reset
MTC timing packet, suppression of COFI-based packets
ToPA output scheme
ToPA tables hold multiple output entries
Single-range output scheme
Number of configurable address ranges for filtering: 2
Supported MTC period encodings: 0x0249
Supported cycle threshold value encodings: 0x3fff
Supported configurable PSB frequency encodings: 0x003f
Time Stamp Counter and Core Crystal Clock Information
Core crystal clock not enumerated
TSC to core crystal clock ratio: 234 / 2
Processor Frequency Information
Base frequency: 2800 MHz
Maximum frequency: 4000 MHz
Bus (reference) frequency: 100 MHz
Maximum extended CPUID leaf: 0x80000008
Extended features, edx:
SYSENTER and SYSEXIT instructions
XD bit
1GB page support
RDTSCP instruction
long mode (EM64T)
Extended features, ecx:
LAHF/SAHF supported in 64-bit mode
LZCNT instruction
3DNow! prefetch instructions
Processor Name: Intel(R) Core(TM) i5-8400 CPU @ 2.80GHz
Advanced Power Management features, edx:
Invariant TSC
Physical address size: 39 bits
Linear address size: 48 bits
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