-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Somebody in the thread at some point said:
| I notice you mention only one chip is currently working as isr source. | But isn't there two independently configurable pins connected to irqs | from that one chip? I didn't dig into the schematic, not sure. We have two physical chips on there, one at the "top" near the earpiece and one at the "bottom" near the mic. The top one is at 45 degrees to the bottom one. Having two is something to do with being able to sense the attitude of the phone in space and not just the position. Both of the chips interrupt the CPU independently at 100Hz when they are being read from, but only one of the CPU interrupts has the magic power to wake from suspend -- the other one is just a regular interrupt that can't do it. But I don't think it will make much difference to the wake threshold scenario since both sensors see a gross action if you pick the phone up or whatever. Separately, there are two INT pins on each chip, but on A6 we only connected one of them to eliminate the pullup. You can select any interrupt function on to either interrupt, it didn't seem that we need more than one at a time. - -Andy -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org iEYEARECAAYFAkf07nAACgkQOjLpvpq7dMrunACeK8MzVSkrsdGHEQQXiwhrZjjJ HQsAn2jyRigiFGp4ShIav4U2RSoMHlgX =7mjn -----END PGP SIGNATURE-----
