From: warmcat <[EMAIL PROTECTED]>
- remove unimplemented S3C MMC voltage scaling API... not used on GTA-01 or -02
- add two platform APIs for Glamo MMC, to set power and check if IRQ used
- GTA-specific stuff should now all be in GTA machine specific files
- UGLY_COUNTERPRODUCTIVE_MAINTAINER_COMMENTS_BE_GONE
Signed-off-by: Andy Green <[EMAIL PROTECTED]>
---
arch/arm/mach-s3c2440/mach-gta02.c | 101 ++++++++++++++++---
drivers/mfd/glamo/glamo-core.c | 191 ++++++++++++++++++++----------------
drivers/mfd/glamo/glamo-core.h | 27 +++++
include/linux/glamofb.h | 5 +
4 files changed, 218 insertions(+), 106 deletions(-)
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c
b/arch/arm/mach-s3c2440/mach-gta02.c
index 0bddcf7..c75e29a 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -231,7 +231,7 @@ static struct pcf50633_platform_data gta02_pcf_pdata = {
},
},
};
-
+#if 0 /* currently unused */
static void cfg_pmu_vrail(struct pmu_voltage_rail *vrail, char *name,
unsigned int flags, unsigned int init,
unsigned int max)
@@ -241,7 +241,7 @@ static void cfg_pmu_vrail(struct pmu_voltage_rail *vrail,
char *name,
vrail->voltage.init = init;
vrail->voltage.max = max;
}
-
+#endif
static void mangle_pmu_pdata_by_system_rev(void)
{
switch (system_rev) {
@@ -395,24 +395,9 @@ static struct s3c2410_platform_nand gta02_nand_info = {
.sets = gta02_nand_sets,
};
-static void gta02_mmc_set_power(unsigned char power_mode, unsigned short vdd)
-{
- printk(KERN_DEBUG "mmc_set_power(power_mode=%u, vdd=%u\n",
- power_mode, vdd);
-
- switch (system_rev) {
- case GTA02v1_SYSTEM_REV:
- case GTA02v2_SYSTEM_REV:
- case GTA02v3_SYSTEM_REV:
- case GTA02v4_SYSTEM_REV:
- /* FIXME */
- break;
- }
-}
-
static struct s3c24xx_mci_pdata gta02_mmc_cfg = {
.gpio_detect = GTA02v1_GPIO_nSD_DETECT,
- .set_power = >a02_mmc_set_power,
+ .set_power = NULL,
.ocr_avail = MMC_VDD_32_33,
};
@@ -652,6 +637,82 @@ static struct s3c2410_hcd_info gta02_usb_info = {
},
};
+static int glamo_irq_is_wired(void)
+{
+ int rc;
+ int count = 0;
+ /*
+ * GTA-02 S-Media IRQs prior to A5 are broken due to a lack of
+ * a pullup on the INT# line. Check for the bad behaviour.
+ */
+ s3c2410_gpio_setpin(S3C2410_GPG4, 0);
+ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP);
+ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_INP);
+ /*
+ * we force it low ourselves for a moment and resume being input.
+ * If there is a pullup, it won't stay low for long. But if the
+ * level converter is there as on < A5 revision, the weak keeper
+ * on the input of the LC will hold the line low indefinitiely
+ */
+ do
+ rc = s3c2410_gpio_getpin(S3C2410_GPG4);
+ while ((!rc) && ((count++) < 10));
+ if (rc) { /* it got pulled back up, it's good */
+ printk(KERN_INFO "Detected S-Media IRQ# pullup, "
+ "enabling interrupt\n");
+ return 0;
+ } else /* Gah we can't work with this level converter */
+ printk(KERN_WARNING "** Detected bad IRQ# circuit found"
+ " on pre-A5 GTA-02: S-Media interrupt disabled **\n");
+ return -ENODEV;
+}
+
+
+static void
+gta02_glamo_mmc_set_power(unsigned char power_mode, unsigned short vdd)
+{
+ int mv = 1650;
+ printk(KERN_DEBUG "mmc_set_power(power_mode=%u, vdd=%u\n",
+ power_mode, vdd);
+
+ switch (system_rev) {
+ case GTA02v1_SYSTEM_REV:
+ case GTA02v2_SYSTEM_REV:
+ break;
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+/* case GTA02v5_SYSTEM_REV: */
+ /* depend on pcf50633 driver init */
+ if (!pcf50633_global)
+ while (!pcf50633_global)
+ msleep(10);
+ switch (power_mode) {
+ case MMC_POWER_ON:
+ case MMC_POWER_UP:
+ /* select and set the voltage */
+ if (vdd > 7) {
+ if (vdd < 23)
+ mv += 300 + (100 * (vdd - 8));
+ else
+ mv = 3500;
+ }
+ pcf50633_voltage_set(pcf50633_global,
+ PCF50633_REGULATOR_HCLDO, mv);
+ msleep(10);
+ pcf50633_onoff_set(pcf50633_global,
+ PCF50633_REGULATOR_HCLDO, 1);
+ msleep(1);
+ break;
+ case MMC_POWER_OFF:
+ pcf50633_onoff_set(pcf50633_global,
+ PCF50633_REGULATOR_HCLDO, 0);
+ msleep(1);
+ break;
+ }
+ break;
+ }
+}
+
/* Smedia Glamo 3362 */
static struct glamofb_platform_data gta02_glamo_pdata = {
@@ -682,6 +743,10 @@ static struct glamofb_platform_data gta02_glamo_pdata = {
},
/* .spi_info = &glamo_spi_cfg, */
.spigpio_info = &glamo_spigpio_cfg,
+
+ /* glamo MMC function platform data */
+ .glamo_set_mci_power = gta02_glamo_mmc_set_power,
+ .glamo_irq_is_wired = glamo_irq_is_wired,
};
static struct resource gta02_glamo_resources[] = {
diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
index fd2ccad..c64136c 100644
--- a/drivers/mfd/glamo/glamo-core.c
+++ b/drivers/mfd/glamo/glamo-core.c
@@ -38,6 +38,8 @@
#include <linux/kernel_stat.h>
#include <linux/spinlock.h>
#include <linux/glamofb.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
#include <asm/io.h>
#include <asm/uaccess.h>
@@ -50,14 +52,6 @@
#include "glamo-regs.h"
#include "glamo-core.h"
-#ifndef UGLY_HACK_BE_GONE
-#ifdef CONFIG_MACH_NEO1973_GTA02
-#include <asm/arch/gpio.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-gpioj.h>
-#endif
-#endif /* UGLY_HACK_BE_GONE */
-
#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
static struct glamo_core *glamo_handle;
@@ -277,6 +271,40 @@ static struct platform_device glamo_fb_dev = {
.num_resources = ARRAY_SIZE(glamo_fb_resources),
};
+static struct resource glamo_mmc_resources[] = {
+ {
+ /* FIXME: those need to be incremented by parent base */
+ .start = GLAMO_REGOFS_MMC,
+ .end = GLAMO_REGOFS_MPROC0 - 1,
+ .flags = IORESOURCE_MEM
+ }, {
+ .start = IRQ_GLAMO_MMC,
+ .end = IRQ_GLAMO_MMC,
+ .flags = IORESOURCE_IRQ,
+ }, { /* our data buffer for MMC transfers */
+ .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
+ .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
+ GLAMO_MMC_BUFFER_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ },
+};
+
+static struct platform_device glamo_mmc_dev = {
+ .name = "glamo-mci",
+ .resource = glamo_mmc_resources,
+ .num_resources = ARRAY_SIZE(glamo_mmc_resources),
+};
+
+struct glamo_mci_pdata glamo_mci_def_pdata = {
+ .gpio_detect = 0,
+ .glamo_set_mci_power = NULL, /* filled in from MFD platform data */
+ .ocr_avail = MMC_VDD_32_33,
+ .glamo_irq_is_wired = NULL, /* filled in from MFD platform data */
+};
+EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
+
+
+
static void mangle_mem_resources(struct resource *res, int num_res,
struct resource *parent)
{
@@ -366,7 +394,8 @@ static void glamo_irq_demux_handler(unsigned int irq,
struct irq_desc *desc)
irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
for (i = 0; i < 9; i++)
if (irqstatus & (1 << i))
- desc_handle_irq(irq, irq_desc+IRQ_GLAMO(i));
+ desc_handle_irq(IRQ_GLAMO(0) + i,
+ irq_desc + IRQ_GLAMO(0) + i);
} while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
@@ -428,6 +457,8 @@ int glamo_engine_enable(struct glamo_core *glamo, enum
glamo_engine engine)
GLAMO_HOSTBUS2_MMIO_EN_CQ);
break;
/* FIXME: Implementation */
+ default:
+ break;
}
spin_unlock(&glamo->lock);
@@ -560,7 +591,6 @@ int glamo_engine_reclock(struct glamo_core *glamo,
if (val) {
val--;
- printk(KERN_INFO "-------------- engine reclock val = %d\n",
val);
reg_set_bit_mask(glamo, reg, mask, val);
msleep(5); /* wait some time to stabilize */
@@ -603,60 +633,71 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_CLOCK_LCD, 0x1000 },
{ GLAMO_REG_CLOCK_MMC, 0x1000 },
{ GLAMO_REG_CLOCK_ISP, 0x1000 },
- { GLAMO_REG_CLOCK_ISP, 0x2000 },
+ { GLAMO_REG_CLOCK_ISP, 0x3000 },
{ GLAMO_REG_CLOCK_JPEG, 0x1000 },
{ GLAMO_REG_CLOCK_3D, 0x1000 },
- { GLAMO_REG_CLOCK_3D, 0x2000 },
+ { GLAMO_REG_CLOCK_3D, 0x3000 },
{ GLAMO_REG_CLOCK_2D, 0x1000 },
- { GLAMO_REG_CLOCK_2D, 0x2000 },
+ { GLAMO_REG_CLOCK_2D, 0x3000 },
{ GLAMO_REG_CLOCK_RISC1, 0x1000 },
{ GLAMO_REG_CLOCK_MPEG, 0x3000 },
{ GLAMO_REG_CLOCK_MPEG, 0x3000 },
- { GLAMO_REG_CLOCK_MPROC, 0x100f },
+ { GLAMO_REG_CLOCK_MPROC, 0x1000 },
{ 0xfffe, 1 },
{ GLAMO_REG_CLOCK_HOST, 0x0000 },
{ GLAMO_REG_CLOCK_MEMORY, 0x0000 },
- { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
{ GLAMO_REG_CLOCK_LCD, 0x0000 },
{ GLAMO_REG_CLOCK_MMC, 0x0000 },
-// { GLAMO_REG_CLOCK_ISP, 0x0000 },
-// { GLAMO_REG_CLOCK_ISP, 0x0000 },
-// { GLAMO_REG_CLOCK_JPEG, 0x0000 },
-// { GLAMO_REG_CLOCK_3D, 0x0000 },
-// { GLAMO_REG_CLOCK_3D, 0x0000 },
+#if 0
+/* unused engines must be left in reset to stop MMC block read "blackouts" */
+ { GLAMO_REG_CLOCK_ISP, 0x0000 },
+ { GLAMO_REG_CLOCK_ISP, 0x0000 },
+ { GLAMO_REG_CLOCK_JPEG, 0x0000 },
+ { GLAMO_REG_CLOCK_3D, 0x0000 },
+ { GLAMO_REG_CLOCK_3D, 0x0000 },
{ GLAMO_REG_CLOCK_2D, 0x0000 },
{ GLAMO_REG_CLOCK_2D, 0x0000 },
-// { GLAMO_REG_CLOCK_RISC1, 0x0000 },
-// { GLAMO_REG_CLOCK_MPEG, 0x0000 },
-// { GLAMO_REG_CLOCK_MPEG, 0x0000 },
- { GLAMO_REG_CLOCK_MPROC, 0x000f },
+ { GLAMO_REG_CLOCK_RISC1, 0x0000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x0000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x0000 },
+ { GLAMO_REG_CLOCK_MPROC, 0x0000 },
{ 0xfffe, 1 },
+#endif
{ GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
{ GLAMO_REG_PLL_GEN3, 0x09c3 }, /* 80MHz */
- { 0xfffe, 300 },
- { GLAMO_REG_IRQ_ENABLE, 0x01ff }, /* all 9 irqs, irq to base */
+ { 0xfffe, 30 },
+ /*
+ * b9 of this register MUST be zero to get any interrupts on INT#
+ * the other set bits enable all the engine interrupt sources
+ */
+ { GLAMO_REG_IRQ_ENABLE, 0x01ff },
{ GLAMO_REG_CLOCK_GEN6, 0x2000 },
{ GLAMO_REG_CLOCK_GEN7, 0x0101 },
{ GLAMO_REG_CLOCK_GEN8, 0x0100 },
{ GLAMO_REG_CLOCK_HOST, 0x000d },
- { 0x200, 0x0ef0 },
- { 0x202, 0x07ff },
+ { 0x200, 0x0cf0 /* 0x0ef0 */ },
+ { 0x202, 0x0298 /* 0x07ff */ },
{ 0x212, 0x0000 },
{ 0x214, 0x4000 },
{ 0x216, 0xf00e },
- { GLAMO_REG_MEM_TYPE, 0x0874 },
- { GLAMO_REG_MEM_GEN, 0xafaf },
- { GLAMO_REG_MEM_TIMING1, 0x0108 },
- { GLAMO_REG_MEM_TIMING2, 0x0010 },
+ { GLAMO_REG_MEM_TYPE, 0x0874 }, /* 8MB, 16 word pg wr+rd */
+ { GLAMO_REG_MEM_GEN, 0xbfbf }, /* 63 grants min + max */
+ /*
+ * the register below originally 0x0108 makes unreliable Glamo MMC
+ * write operations. Cranked to 0x05ad to add a wait state, the
+ * unreliability is not seen after 4GB of write / read testing
+ */
+ { GLAMO_REG_MEM_TIMING1, 0x05ad },
+ { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
{ GLAMO_REG_MEM_TIMING3, 0x0000 },
- { GLAMO_REG_MEM_TIMING4, 0x0000 },
+ { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
{ GLAMO_REG_MEM_TIMING5, 0x0000 },
{ GLAMO_REG_MEM_TIMING6, 0x0000 },
{ GLAMO_REG_MEM_TIMING7, 0x0000 },
- { GLAMO_REG_MEM_TIMING8, 0x1002 },
- { GLAMO_REG_MEM_TIMING9, 0x6006 },
+ { GLAMO_REG_MEM_TIMING8, 0x1000 },
+ { GLAMO_REG_MEM_TIMING9, 0x6000 },
{ GLAMO_REG_MEM_TIMING10, 0x00ff },
- { GLAMO_REG_MEM_TIMING11, 0x0001 },
+ { GLAMO_REG_MEM_TIMING11, 0x0000 },
{ GLAMO_REG_MEM_POWER1, 0x0020 },
{ GLAMO_REG_MEM_POWER2, 0x0000 },
{ GLAMO_REG_MEM_DRAM1, 0x0000 },
@@ -664,11 +705,11 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_MEM_DRAM1, 0xc100 },
{ 0xfffe, 1 },
{ GLAMO_REG_MEM_DRAM1, 0xe100 },
- { GLAMO_REG_MEM_DRAM2, 0x01d6 },
- { GLAMO_REG_CLOCK_MEMORY, 0x000a },
-// { GLAMO_REG_CLOCK_MEMORY, 0x000b },
+ { GLAMO_REG_MEM_DRAM2, 0x0155 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x000f },
};
+
#if 0 /* MM370 */
static const struct glamo_script regs_vram_2mb = {
{ GLAMO_REG_CLOCK_MEMORY, 0x3aaa },
@@ -780,6 +821,7 @@ static void glamo_power(struct glamo_core *glamo,
spin_unlock(&glamo->lock);
}
+#if 0
#define MEMDETECT_RETRY 6
static unsigned int detect_memsize(struct glamo_core *glamo)
{
@@ -841,6 +883,7 @@ static unsigned int detect_memsize(struct glamo_core *glamo)
return 0;
}
+#endif
/* Find out if we can support this version of the Glamo chip */
static int glamo_supported(struct glamo_core *glamo)
@@ -887,7 +930,6 @@ static int glamo_supported(struct glamo_core *glamo)
static int __init glamo_probe(struct platform_device *pdev)
{
int rc, irq;
- int count = 0;
struct glamo_core *glamo;
if (glamo_handle) {
@@ -922,8 +964,22 @@ static int __init glamo_probe(struct platform_device *pdev)
glamo_core_dev.resources[1].end = glamo->irq;
platform_device_register(&glamo_core_dev);
#endif
+ /* only remap the generic, hostbus and memory controller registers */
+ glamo->base = ioremap(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
+ if (!glamo->base) {
+ dev_err(&pdev->dev, "failed to ioremap() memory region\n");
+ goto out_free;
+ }
+
+ /* bring MCI specific stuff over from our MFD platform data */
+ glamo_mci_def_pdata.glamo_set_mci_power =
+ glamo->pdata->glamo_set_mci_power;
+ glamo_mci_def_pdata.glamo_irq_is_wired =
+ glamo->pdata->glamo_irq_is_wired;
glamo_mmc_dev.dev.parent = &pdev->dev;
+ /* we need it later to give to the engine enable and disable */
+ glamo_mci_def_pdata.pglamo = glamo;
mangle_mem_resources(glamo_mmc_dev.resource,
glamo_mmc_dev.num_resources, glamo->mem);
platform_device_register(&glamo_mmc_dev);
@@ -968,13 +1024,6 @@ static int __init glamo_probe(struct platform_device
*pdev)
goto out_free;
}
- /* only remap the generic, hostbus and memory controller registers */
- glamo->base = ioremap(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
- if (!glamo->base) {
- dev_err(&pdev->dev, "failed to ioremap() memory region\n");
- goto out_free;
- }
-
if (!glamo_supported(glamo)) {
dev_err(&pdev->dev, "This Glamo is not supported\n");
goto out_free;
@@ -989,53 +1038,21 @@ static int __init glamo_probe(struct platform_device
*pdev)
glamo_pll_rate(glamo, GLAMO_PLL1),
glamo_pll_rate(glamo, GLAMO_PLL2));
- /* FIXME: do we need to request_irq() it ? */
-
- dev_dbg(&glamo->pdev->dev, "interrupts\n");
for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
set_irq_chip(irq, &glamo_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
-#ifndef UGLY_HACK_BE_GONE
- /*
- * GTA-02 S-Media IRQs prior to A5 are broken due to a lack of
- * a pullup on the INT# line. Check for the bad behaviour.
- */
- s3c2410_gpio_setpin(S3C2410_GPG4, 0);
- s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP);
- s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_INP);
- /*
- * we force it low ourselves for a moment and resume being input.
- * If there is a pullup, it won't stay low for long. But if the
- * level converter is there as on < A5 revision, the weak keeper
- * on the input of the LC will hold the line low indefinitiely
- */
- do {
- rc = s3c2410_gpio_getpin(S3C2410_GPG4);
- } while ((!rc) && ((count++) < 10));
-
- if (rc) { /* it got pulled back up, it's good */
- dev_info(&glamo->pdev->dev, "Detected S-Media IRQ# pullup, "
- "enabling interrupt\n");
- glamo->irq_works = 1;
- } else { /* Gah we can't work with this level converter */
- dev_warn(&glamo->pdev->dev, "** Detected bad IRQ# circuit found"
- " on pre-A5 GTA-02: S-Media interrupt disabled **\n");
- glamo->irq_works = 0;
- }
-#endif /* UGLY_HACK_BE_GONE */
-
- if (!glamo->irq || !glamo->irq_works)
- dev_warn(&glamo->pdev->dev, "No IRQ support on this
hardware!\n");
- else {
- dev_dbg(&glamo->pdev->dev, "chained\n");
- set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
- dev_dbg(&glamo->pdev->dev, "type\n");
- set_irq_type(glamo->irq, IRQT_FALLING);
+ if (glamo->pdata->glamo_irq_is_wired) {
+ if (!glamo->pdata->glamo_irq_is_wired()) {
+ set_irq_chained_handler(glamo->irq,
+ glamo_irq_demux_handler);
+ set_irq_type(glamo->irq, IRQT_FALLING);
+ glamo->irq_works = 1;
+ } else
+ glamo->irq_works = 0;
}
-
return 0;
out_free:
diff --git a/drivers/mfd/glamo/glamo-core.h b/drivers/mfd/glamo/glamo-core.h
index f5f6eb4..4428c55 100644
--- a/drivers/mfd/glamo/glamo-core.h
+++ b/drivers/mfd/glamo/glamo-core.h
@@ -1,9 +1,23 @@
#ifndef __GLAMO_CORE_H
#define __GLAMO_CORE_H
+/* for the time being, we put the on-screen framebuffer into the lowest
+ * VRAM space. This should make the code easily compatible with the various
+ * 2MB/4MB/8MB variants of the Smedia chips */
+#define GLAMO_OFFSET_VRAM 0x800000
+#define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM)
+
+/* we only allocate the minimum possible size for the framebuffer to make
+ * sure we have sufficient memory for other functions of the chip */
+//#define GLAMO_FB_SIZE (640*480*4) /* == 0x12c000 */
+#define GLAMO_INTERNAL_RAM_SIZE 0x800000
+#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
+#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
+
+
struct glamo_core {
int irq;
- int irq_works; /* 0 means PCB does not support Glamo IRQ - UGLY HACK */
+ int irq_works; /* 0 means PCB does not support Glamo IRQ */
struct resource *mem;
struct resource *mem_core;
void __iomem *base;
@@ -45,6 +59,17 @@ enum glamo_engine {
__NUM_GLAMO_ENGINES
};
+struct glamo_mci_pdata {
+ struct glamo_core * pglamo;
+ unsigned int gpio_detect;
+ unsigned int gpio_wprotect;
+ unsigned long ocr_avail;
+ void (*glamo_set_mci_power)(unsigned char power_mode,
+ unsigned short vdd);
+ int (*glamo_irq_is_wired)(void);
+};
+
+
int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
diff --git a/include/linux/glamofb.h b/include/linux/glamofb.h
index f5028b5..24742a2 100644
--- a/include/linux/glamofb.h
+++ b/include/linux/glamofb.h
@@ -26,6 +26,11 @@ struct glamofb_platform_data {
struct glamo_spi_info *spi_info;
struct glamo_spigpio_info *spigpio_info;
struct glamo_core *glamo;
+
+ /* glamo mmc platform specific info */
+ void (*glamo_set_mci_power)(unsigned char power_mode,
+ unsigned short vdd);
+ int (*glamo_irq_is_wired)(void);
};
void glamofb_cmd_mode(struct glamofb_handle *gfb, int on);
