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Somebody in the thread at some point said:
> I wrote:
>> When I first booted 2.6.24 o GTA02v3, I got bit rot in the GTA02
>> framebuffer ("noise" appearing in short lines, maybe some ~20-80
>> pixels long), but this disappeared on subsequent tries.
>
> I spoke to early. It's back:
> http://people.openmoko.org/werner/bitrot.png
>
> This device's battery is low. Maybe it's because of that. I looked
> at 3V3 and 1V8, and they look stable, though.
Werner I think this one is on me -- try the attached patch.
I threshed around for days trying to fix a problem with the Glamo MMC
corrupting packets internal to the chip by changing memory settings
amongst other things. Afterwards it turned out that problem was a
physical issue on my PCB. So this patch reverts those meddlings.
- -Andy
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adjust-glamo-intl-timings-back.patch
From: warmcat <[EMAIL PROTECTED]>
---
build | 1 -
drivers/mfd/glamo/glamo-core.c | 29 +++++++++++++++--------------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/build b/build
index 7e61ea2..a3af85e 100755
--- a/build
+++ b/build
@@ -11,4 +11,3 @@ if make -j5 ARCH=arm; then
else
exit 1
fi
-
diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
index 476f8df..80d9795 100644
--- a/drivers/mfd/glamo/glamo-core.c
+++ b/drivers/mfd/glamo/glamo-core.c
@@ -627,7 +627,7 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_CLOCK_RISC1, 0x1000 },
{ GLAMO_REG_CLOCK_MPEG, 0x3000 },
{ GLAMO_REG_CLOCK_MPEG, 0x3000 },
- { GLAMO_REG_CLOCK_MPROC, 0x1000 },
+ { GLAMO_REG_CLOCK_MPROC, 0x100f },
{ 0xfffe, 1 },
{ GLAMO_REG_CLOCK_HOST, 0x0000 },
{ GLAMO_REG_CLOCK_MEMORY, 0x0000 },
@@ -645,12 +645,12 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_CLOCK_RISC1, 0x0000 },
{ GLAMO_REG_CLOCK_MPEG, 0x0000 },
{ GLAMO_REG_CLOCK_MPEG, 0x0000 },
- { GLAMO_REG_CLOCK_MPROC, 0x0000 },
- { 0xfffe, 1 },
#endif
+ { GLAMO_REG_CLOCK_MPROC, 0x000f },
+ { 0xfffe, 1 },
{ GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
{ GLAMO_REG_PLL_GEN3, 0x09c3 }, /* 80MHz */
- { 0xfffe, 30 },
+ { 0xfffe, 50 },
/*
* b9 of this register MUST be zero to get any interrupts on INT#
* the other set bits enable all the engine interrupt sources
@@ -660,29 +660,29 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_CLOCK_GEN7, 0x0101 },
{ GLAMO_REG_CLOCK_GEN8, 0x0100 },
{ GLAMO_REG_CLOCK_HOST, 0x000d },
- { 0x200, 0x0cf0 /* 0x0ef0 */ },
- { 0x202, 0x0298 /* 0x07ff */ },
+ { 0x200, 0x0ef0 },
+ { 0x202, 0x07ff },
{ 0x212, 0x0000 },
{ 0x214, 0x4000 },
{ 0x216, 0xf00e },
{ GLAMO_REG_MEM_TYPE, 0x0874 }, /* 8MB, 16 word pg wr+rd */
- { GLAMO_REG_MEM_GEN, 0xbfbf }, /* 63 grants min + max */
+ { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
/*
* the register below originally 0x0108 makes unreliable Glamo MMC
* write operations. Cranked to 0x05ad to add a wait state, the
* unreliability is not seen after 4GB of write / read testing
*/
- { GLAMO_REG_MEM_TIMING1, 0x05ad },
- { GLAMO_REG_MEM_TIMING2, 0x0011 }, /* Taa = 3 MCLK */
+ { GLAMO_REG_MEM_TIMING1, 0x0108 },
+ { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
{ GLAMO_REG_MEM_TIMING3, 0x0000 },
{ GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
{ GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
{ GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
{ GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
- { GLAMO_REG_MEM_TIMING8, 0x1008 }, /* MCLK delay, was 0x1000 */
- { GLAMO_REG_MEM_TIMING9, 0x6000 },
+ { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
+ { GLAMO_REG_MEM_TIMING9, 0x6006 },
{ GLAMO_REG_MEM_TIMING10, 0x00ff },
- { GLAMO_REG_MEM_TIMING11, 0x0000 },
+ { GLAMO_REG_MEM_TIMING11, 0x0001 },
{ GLAMO_REG_MEM_POWER1, 0x0020 },
{ GLAMO_REG_MEM_POWER2, 0x0000 },
{ GLAMO_REG_MEM_DRAM1, 0x0000 },
@@ -690,8 +690,8 @@ static struct glamo_script glamo_init_script[] = {
{ GLAMO_REG_MEM_DRAM1, 0xc100 },
{ 0xfffe, 1 },
{ GLAMO_REG_MEM_DRAM1, 0xe100 },
- { GLAMO_REG_MEM_DRAM2, 0x0155 },
- { GLAMO_REG_CLOCK_MEMORY, 0x000f },
+ { GLAMO_REG_MEM_DRAM2, 0x01d6 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x000b },
};
@@ -781,6 +781,7 @@ static void glamo_power(struct glamo_core *glamo,
/* spin until PLL1 lock */
while (!(__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 1))
;
+ /* FIXME: reset pll's */
break;
case GLAMO_POWER_STANDBY:
/* enable memory self-refresh */
