A discussion about bluetooth and VOIP that was held.
--- Begin Message ---
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Somebody in the thread at some point said:
|> | have bluetooth wired on GTA02 we cannot do a VOIP call with a bluetooth
|> | headset. There just isnt enough connectivity within the codec.
|>
|> What is the problem here, we can't access the PCM "VX" interface in and
|> out from CPU? Huh? That's all we need?
|>
| There is no digital connection between the two interfaces on the codec
| and there is not enough analogue wires or ADC's to route between the two
| interfaces.
Wow that's BAD! There are a zillion controls in alsamixer but no
routing between the interfaces!
We can use your suggestion and just wire it all up together like CPU and
WM8753 are both master, but set CPU GPIO to forced float when WM8753
drives it, force WM8753 PCM interface tristate (and CPU GPIO into I2S
peripheral mode) when CPU drives it. Zero glue logic needed.
But great job pointing out this shortcoming!
- -Andy
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org
iEYEARECAAYFAkgEtHIACgkQOjLpvpq7dMpf3QCff8dPiYerRHntfprAoB9hfhsC
1bkAnRogP2PzX+w3e/+Y+gnL5B1bP7UE
=McgP
-----END PGP SIGNATURE-----
--- End Message ---
--- Begin Message ---
On Tue, Apr 15, 2008 at 02:58:17PM +0100, Andy Green wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Somebody in the thread at some point said:
>
> |> | have bluetooth wired on GTA02 we cannot do a VOIP call with a
> bluetooth
> |> | headset. There just isnt enough connectivity within the codec.
> |>
> |> What is the problem here, we can't access the PCM "VX" interface in and
> |> out from CPU? Huh? That's all we need?
> |>
> | There is no digital connection between the two interfaces on the codec
> | and there is not enough analogue wires or ADC's to route between the two
> | interfaces.
>
> Wow that's BAD! There are a zillion controls in alsamixer but no
> routing between the interfaces!
>
> We can use your suggestion and just wire it all up together like CPU and
> WM8753 are both master, but set CPU GPIO to forced float when WM8753
> drives it, force WM8753 PCM interface tristate (and CPU GPIO into I2S
> peripheral mode) when CPU drives it. Zero glue logic needed.
>
On the s3c24XX CPU the codec and bluetooth always master as the
cpu is crap (cant even make an approximately right frequency) at
generating audio clocks.
I guess similar will be true on the s3c6400.
Graeme
_______________________________________________
gta04 mailing list
[EMAIL PROTECTED]
https://lists.internal.openmoko.org/mailman/listinfo/gta04
--- End Message ---
--- Begin Message ---
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Somebody in the thread at some point said:
|> We can use your suggestion and just wire it all up together like CPU and
|> WM8753 are both master, but set CPU GPIO to forced float when WM8753
|> drives it, force WM8753 PCM interface tristate (and CPU GPIO into I2S
|> peripheral mode) when CPU drives it. Zero glue logic needed.
|>
| On the s3c24XX CPU the codec and bluetooth always master as the
| cpu is crap (cant even make an approximately right frequency) at
| generating audio clocks.
|
| I guess similar will be true on the s3c6400.
It is true there are just some crappy canned division ratios. However
on p36-3 of the SC36400X54_UM_PreliminaryRev0.0_20071019.pdf document it
says:
''Master or slave mode can be selected by setting IMS bit of IISMOD
register. In master mode, I2SSCLK and I2SLRCLK are generated internally
and supplied to external device. Therefore a root clock is needed for
generating I2SSCLK and I2SLRCLK by dividing. The IIS pre-scaler (clock
divider) is employed for generating a root clock with divided frequency
from internal system clock. In external master mode, the root clock can
be fed from IIS external directly. <<<====
The I2SSCLK and I2SLRCLK are supplied from the pin (GPIOs) in slave mode.''
So we can be in master mode at CPU and yet still accept external I2S
clock from Codec.
The WM8753 uses a PLL to generate the special I2S clock, the PLL output
is issues on the CLK1 / CLK2 pins so it is accessible even if the WM8753
I2S side is also in slave.
- -Andy
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org
iEYEARECAAYFAkgEucUACgkQOjLpvpq7dMpveQCfSCv2Z7yT0oxs48V1zF8YRGn/
RdUAn2XbZgo0bFd/5WcbVrKDZsgvcjQg
=JKs7
-----END PGP SIGNATURE-----
--- End Message ---
--- Begin Message ---
On Tue, Apr 15, 2008 at 03:20:59PM +0100, Andy Green wrote:
> It is true there are just some crappy canned division ratios. However
> on p36-3 of the SC36400X54_UM_PreliminaryRev0.0_20071019.pdf document it
> says:
>
> ''Master or slave mode can be selected by setting IMS bit of IISMOD
> register. In master mode, I2SSCLK and I2SLRCLK are generated internally
> and supplied to external device. Therefore a root clock is needed for
> generating I2SSCLK and I2SLRCLK by dividing. The IIS pre-scaler (clock
> divider) is employed for generating a root clock with divided frequency
> from internal system clock. In external master mode, the root clock can
> be fed from IIS external directly. <<<====
>
> The I2SSCLK and I2SLRCLK are supplied from the pin (GPIOs) in slave mode.''
>
> So we can be in master mode at CPU and yet still accept external I2S
> clock from Codec.
>
> The WM8753 uses a PLL to generate the special I2S clock, the PLL output
> is issues on the CLK1 / CLK2 pins so it is accessible even if the WM8753
> I2S side is also in slave.
>
Thanks for that info, I find the s3c6400 pdf hard to read as evince
takes 100% cpu load spewing korean fonts errors.
This mode is how the pxa boards drive wolfson codecs. Its certainly
easier in some respects as when cpu is master you cant lockup waiting
for codec.
Graeme
_______________________________________________
gta04 mailing list
[EMAIL PROTECTED]
https://lists.internal.openmoko.org/mailman/listinfo/gta04
--- End Message ---
