-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Somebody in the thread at some point said: | Andy Green wrote: | ... |> In practical terms, FIQ on S3C24xx works that you can cherrypick ONE |> normal interrupt source and elevate it to "FIQ power"... | | This problem may well exist on the GTA02 as well (although it has a | deeper FIFO, I suspect that will only serve to mask the problem so that | in accordance with Murphy's law, it will happen only when correct | operation is most needed). Does the fact that the GTA02 already uses | the FIQ preclude this solution for that device as well, or is there some | other consideration for shared FIQ use?
The S3C2442 datasheet has a big NOTE by that register saying to only enable one source. I guess the issue is that the ARM can't deal with FIQ reentrancy, it has a single set of FIQ shadow registers for high speed context switching: once you started using them if another FIQ comes you are in trouble. If I understood it the problem only comes during resume... I guess the big question is, is all that is needed to make the problem a long period with interrupts off? If that's all it takes, I would wonder if one of the resume handlers is spinning at a bad time, eg, LCM ASIC one has mdelay() in there IIRC. - -Andy -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org iEYEARECAAYFAkgV44AACgkQOjLpvpq7dMrtxwCghK4wfM+63NV2YRaF6c23kj0/ JKsAn1RSgjNDgRJBGhiBlgzMYaDAHtb7 =Gc28 -----END PGP SIGNATURE-----
