the init uart code:
/* init uart0 */
ldr r0, =0x50000000
mov r1, #0x03
str r1, [r0] /* Line control register : Normal,No
parity,1 stop,8 bits */
/* UCON register
:
* [11:10] [9] [8] [7]
[6] [5] [4] [3:2]
[1:0]
* Clock Sel, Tx Int, Rx Int, Rx Time Out, Rx err, Loop-back,
Send break, Transmit Mode, Receive Mode
* 00 1 0 , 0
1 0 0 , 01
01
* PCLK Level Pulse Disable Generate
Normal Normal Interrupt or Polling
*/
ldr r1, =0x245
str r1, [r0, #0x04]
mov r1, #0x00
str r1, [r0, #0x08] /* UART channel 0 FIFO control register,
FIFO disable */
mov r1,
#0x00
str r1, [r0, #0x0c] /* UART channel 0 MODEM control
register, AFC disable */
mov r1, #0x11
str r1, [r0, #0x28] /* ubrdiv */
Andy Green wrote:
| 2. config uart clock source as PCLK, 16Mhz,
i calculate the PCLK by hand but it is not 16Mhz,
i use follow code calculate the PCLK ( calc_pclk.c )
the output is :
MPLLCON_val: 581745
MPLL: 581745
PCLK: 33333300
ubrdiv: 17
so i set ubrdiv = 0x11
Make sure you set the GPIO registers for these pins to be in peripheral
mode not GPIO. See GPHCON.
i change the start.S code
/*
* === PORT H
GROUP
* Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3
GPH2 GPH1 GPH0
* Signal : CLKOUT1 CLKOUT0 UEXTCLK nCTS1 nRTS1 RXD1 TXD1
RXD0 TXD0 nRTS0 nCTS0
* Binary : 10 , 10 10 ,
11 11 , 10 10 , 10 10 , 10
10
*/
ldr r0, =0x56000070
ldr r1, =0x2afaaa
str r1, [r0]
There's also a peripheral clock mask register CLKCON, it says it resets
to all enabled though.
i think i do that:
/* init uart0 */
ldr r0, =0x4c00000c /* clkcon */
ldr r1, =0xffff0 /* all clocks on */
str r1, [r0]
i try the UART0 UART1 and UART2 , all now work,
-------------------------------------------------------------------------------
the sent code :
#define UTXH (*(volatile unsigned char *)0x50000020)
#define UTRSTAT (*(volatile unsigned char *)0x50000010)
/*
* Output a single byte to the serial
port.
*/
void serial_putc (const char c)
{
while (!(UTRSTAT & 0x2));
delay(10);
UTXH = c;
}
-----------------------------------------------------------------------
another question:
first i use "sudo modprobe ftdi_sio vendor=0x1457 product=0x5118"
then there are /dev/ttyUSB0 in my PC (something it is /dev/ttyUSB1, and
there no /dev/ttyUSB0)
is the mean if the code is work,then i can get something from /dev/ttyUSB0 ?
there are three UART in s3c2442, which i should use ,
or it is doesn't matter which i use, and h
i really don't know what wrong of this code :-(
#include <stdio.h>
# define CLKDIVN_val (7)
# define CAMDIVN_val (0)
# define CONFIG_SYS_CLK_FREQ (12000000)/* the GTA02 has this input clock */
# define MPLL ((142 << 12) + (7 << 4) + 1)
# define BAUDRATE (115200)
typedef unsigned long ulong;
static ulong get_PLLCLK(int pllreg)
{
ulong r, m, p, s;
if (pllreg == MPLL){
r = MPLL;
}
m = ((r & 0xFF000) >> 12) + 8;
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
/* To avoid integer overflow, changed the calc order */
if (pllreg == MPLL)
return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
else
return ( m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
}
ulong get_FCLK(void)
{
return(get_PLLCLK(MPLL));
}
ulong get_HCLK(void)
{
switch (CLKDIVN_val & 0x6) {
case 0x0:
return get_FCLK();
case 0x2:
return get_FCLK()/2;
case 0x4:
return (CAMDIVN_val & 0x200) ? get_FCLK()/8 : get_FCLK()/4;
case 0x6:
return (CAMDIVN_val & 0x100) ? get_FCLK()/6 : get_FCLK()/3;
}
return 0;
}
ulong get_PCLK(void)
{
return((CLKDIVN_val & 0x1) ? get_HCLK()/2 : get_HCLK());
}
int main()
{
printf("MPLLCON_val: %d\n", ((142 << 12) + (7 << 4) + 1));
/* printf("UPLLCON_val: %d\n", (( 88 << 12) + (8 << 4) + 2));
printf("%d\n", (( 26 << 12) + (4 << 4) + 1)); */
printf("MPLL: %d\n",MPLL);
printf("PCLK: %d\n",(int) get_PCLK());
int reg =( (int) get_PCLK() ) / (16 * BAUDRATE) - 1;
printf("ubrdiv: %d\n",reg);
return 0;
}
