[PATCH 07/13] qi-s3c2442-enable-d-cache.patch

[Andy Green]

Seems we have no D-Cache enabled before?  Also defeat AUX as EINT

Signed-off-by: Andy Green <[EMAIL PROTECTED]>
---

 src/cpu/s3c2442/gta02.c |    6 +++++-
 src/cpu/s3c2442/start.S |    2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/cpu/s3c2442/gta02.c b/src/cpu/s3c2442/gta02.c
index 2ea520a..7b78b81 100644
--- a/src/cpu/s3c2442/gta02.c
+++ b/src/cpu/s3c2442/gta02.c
@@ -168,7 +168,7 @@ void port_init_gta02(void)
         *     Binary :  01      01 ,  01     01  ,     10       10  , 10     10
         */
        /* pulldown on GPF03: TP-4705+debug - debug conn will float */
-       rGPFCON = 0x0000AAAA;
+       rGPFCON = 0x00008AAA;
        rGPFUP = 0x000000FF & ~(1 << 3);
        rGPFDAT = 0x00000000;
 
@@ -366,6 +366,10 @@ static void close_gta02(void)
        /* set I2C GPIO back to peripheral unit */
 
        (bb_s3c24xx.close)();
+
+       /* aux back to being EINT */
+       rGPFCON = 0x0000AAAA;
+
 }
 
 static u8 get_ui_keys_gta02(void)
diff --git a/src/cpu/s3c2442/start.S b/src/cpu/s3c2442/start.S
index eaab799..6ff9194 100644
--- a/src/cpu/s3c2442/start.S
+++ b/src/cpu/s3c2442/start.S
@@ -298,7 +298,7 @@ cpu_init_crit:
        bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
        bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
        orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
-       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
+       orr     r0, r0, #0x00005000     @ set bits 14, 12 D and I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
        /*