This is an automated email from Gerrit. Antonio Borneo ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/231
-- gerrit commit 6b270fa30501028076e00472e87e9f7e760b80d2 Author: Antonio Borneo <[email protected]> Date: Fri Nov 18 13:10:00 2011 +0800 TCL: Add board file for EVAL_SPEAr320CPU Initial support for SPEAr320 chip and for evaluation board named EVAL_SPEAr320CPU. Change-Id: I85524655769bcc610294a26db47a7a399256fbb7 Signed-off-by: Antonio Borneo <[email protected]> diff --git a/tcl/board/spear320cpu.cfg b/tcl/board/spear320cpu.cfg new file mode 100644 index 0000000..71efca7 --- /dev/null +++ b/tcl/board/spear320cpu.cfg @@ -0,0 +1,44 @@ +# Configuration for the ST SPEAr320 CPU board +# EVAL_SPEAr320CPU Rev. 2.0 +# http://www.st.com/spear +# +# Date: 2011-11-18 +# Author: Antonio Borneo <[email protected]> + +# The standard board has JTAG SRST not connected. +# This script targets such boards using quirky code to bypass the issue. + + +source [find mem_helper.tcl] +source [find target/spear3xx.cfg] +source [find chip/st/spear/spear3xx_ddr.tcl] +source [find chip/st/spear/spear3xx.tcl] + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + + +# Serial NOR on SMI CS0. 8Mbyte. +set _FLASHNAME1 $_CHIPNAME.snor +flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME + +if { [info exists BOARD_HAS_SRST] } { + # Modified board has SRST on JTAG connector + reset_config trst_and_srst separate srst_gates_jtag \ + trst_push_pull srst_open_drain +} else { + # Standard board has no SRST on JTAG connector + reset_config trst_only separate srst_gates_jtag trst_push_pull + source [find chip/st/spear/quirk_no_srst.tcl] +} + +$_TARGETNAME configure -event reset-init { spear320cpu_init } + +proc spear320cpu_init {} { + reg pc 0xffff0020; # loop forever + + sp3xx_clock_default + sp3xx_common_init + sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $DDR_CHIPS + sp320_init +} diff --git a/tcl/board/spear320cpu_mod.cfg b/tcl/board/spear320cpu_mod.cfg new file mode 100644 index 0000000..0dd3d6c --- /dev/null +++ b/tcl/board/spear320cpu_mod.cfg @@ -0,0 +1,25 @@ +# Configuration for the ST SPEAr320 Evaluation board +# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector +# http://www.st.com/spear +# +# List of board modifications to enable SRST, as reported in +# ST Application Note (FIXME: add reference). +# - Modifications on the bottom layer: +# 1. replace reset chip U7 with a STM6315SDW13F; +# 2. add 0 ohm resistor R45. It is located close to JTAG connector. +# 3. add a 10K ohm pull-up resistor on the reset wire named as +# POWERGOOD in the schematic. +# +# The easier way to do modification 3, is to use a resistor in package +# 0603 or 0402 and solder it between R15 and R45: +# - one pad soldered with the pad of R15 connected to 3.3V (this +# is the pad of R15 closer to R45) +# - the other pad soldered with the nearest pad of R45. +# +# Date: 2011-11-18 +# Author: Antonio Borneo <[email protected]> + + +# Modified boards has SRST on JTAG connector +set BOARD_HAS_SRST 1 +source [find board/spear320evb.cfg] diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl index ce9e0ca..ef38841 100644 --- a/tcl/chip/st/spear/spear3xx.tcl +++ b/tcl/chip/st/spear/spear3xx.tcl @@ -120,3 +120,10 @@ proc sp310_emi_init {} { mww 0x4f000014 0x0000000e ;# control_0_reg mww 0x4f000094 0x0000003f ;# ack_reg } + + +# Specific init scripts for ST SPEAr320 +proc sp320_init {} { + mww 0xb300000c 0xffffac04 ;# RAS function enable + mww 0xb3000010 0x00000001 ;# RAS mode select +} -- ------------------------------------------------------------------------------ All the data continuously generated in your IT infrastructure contains a definitive record of customers, application performance, security threats, fraudulent activity, and more. Splunk takes this data and makes sense of it. IT sense. And common sense. http://p.sf.net/sfu/splunk-novd2d _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
