Hello, I am new to OpenOCD and I am trying to debug TI's DM8148 EVM board using OpenOCD and Flyswatter2. After setting up the ICEPICK-D OpenOCD sees the Cortex A8 but it will not halt. A work in progress configuration file is included below.
According to TI, setting up the ICEPICK following these instructions <http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf> should allow the CPU to halt (unlike the OMAP3530 which requires an extra step to assert DBGEN). However, using the aforementioned instructions (see icepick_d_tapenable in the configuration file) results in: [...] Info : JTAG tap: dm8148.jrc tap/device found: 0x3b8f202f (mfg: 0x017, part: 0xb8f2, ver: 0x3) Info : JTAG tap: dm8148.dap enabled Warn : Invalid ACK 0x6 in JTAG-DP transaction Polling target failed, GDB will be halted. Polling again in 100ms Polling target failed, GDB will be halted. Polling again in 300ms Polling target failed, GDB will be halted. Polling again in 700ms [...] and the Cortex A8 is not visible. While, if I use the ICEPICK-C setup that comes with OpenOCD or an ICEPICK-D setup converted from a BDI-3000 configuration file (see icepick_d_tapenable_bdi in the configuration file), the Cortex A8 DAP is visible but the CPU will not halt: [...] Debug: 320 5507 core.c:1530 jtag_init_reset(): Initializing with hard TRST+SRST reset Debug: 321 5507 ft2232.c:1614 flyswatter2_reset(): trst: 1, srst: 0, low_output: 0x28, low_direction: 0x7b Debug: 322 5508 core.c:732 jtag_add_reset(): TRST line asserted Debug: 323 5508 ft2232.c:1614 flyswatter2_reset(): trst: 0, srst: 0, low_output: 0x38, low_direction: 0x7b Debug: 324 5509 core.c:737 jtag_add_reset(): TRST line released Debug: 325 5509 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 326 5509 tcl.c:655 jtag_tap_handle_event(): JTAG tap: dm8148.jrc event: 0 (post-reset) action: runtest 1000 Debug: 327 5509 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_runtest 1000 Debug: 328 5509 command.c:151 script_debug(): command - runtest ocd_runtest 1000 Debug: 330 5510 core.c:1435 jtag_init_inner(): Init JTAG chain Debug: 331 5510 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 332 5510 tcl.c:655 jtag_tap_handle_event(): JTAG tap: dm8148.jrc event: 0 (post-reset) action: runtest 1000 Debug: 333 5510 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_runtest 1000 Debug: 334 5510 command.c:151 script_debug(): command - runtest ocd_runtest 1000 Debug: 336 5511 core.c:1055 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 337 5511 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 338 5511 tcl.c:655 jtag_tap_handle_event(): JTAG tap: dm8148.jrc event: 0 (post-reset) action: runtest 1000 Debug: 339 5511 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_runtest 1000 Debug: 340 5511 command.c:151 script_debug(): command - runtest ocd_runtest 1000 Info : 342 5513 core.c:955 jtag_examine_chain_display(): JTAG tap: dm8148.jrc tap/device found: 0x3b8f202f (mfg: 0x017, part: 0xb8f2, ver: 0x3) Debug: 343 5513 core.c:1219 jtag_validate_ircapture(): IR capture validation scan Debug: 344 5515 core.c:1280 jtag_validate_ircapture(): dm8148.jrc: IR capture 0x01 Debug: 345 5515 tcl.c:655 jtag_tap_handle_event(): JTAG tap: dm8148.jrc event: 1 (setup) action: jtag tapenable dm8148.dap Debug: 346 5515 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_jtag tapenable dm8148.dap Debug: 347 5515 command.c:151 script_debug(): command - ocd_jtag ocd_jtag tapenable dm8148.dap Debug: 348 5515 tcl.c:655 jtag_tap_handle_event(): JTAG tap: dm8148.dap event: 2 (tap-enable) action: icepick_d_tapenable_bdi dm8148.jrc 12 Debug: 349 5515 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_irscan dm8148.jrc 7 -endstate IRPAUSE Debug: 350 5515 command.c:151 script_debug(): command - irscan ocd_irscan dm8148.jrc 7 -endstate IRPAUSE Debug: 352 5516 command.c:151 script_debug(): command - drscan drscan dm8148.jrc 8 0x89 -endstate DRPAUSE Debug: 353 5519 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_irscan dm8148.jrc 2 -endstate IRPAUSE Debug: 354 5519 command.c:151 script_debug(): command - irscan ocd_irscan dm8148.jrc 2 -endstate IRPAUSE Debug: 356 5520 command.c:151 script_debug(): command - drscan drscan dm8148.jrc 32 81000080 -endstate DRPAUSE Debug: 357 5522 command.c:151 script_debug(): command - drscan drscan dm8148.jrc 32 2885689352 -endstate DRPAUSE Debug: 358 5524 command.c:151 script_debug(): command - drscan drscan dm8148.jrc 32 0xe0002008 -endstate DRPAUSE Debug: 359 5526 command.c:151 script_debug(): command - drscan drscan dm8148.jrc 32 2885689608 -endstate DRPAUSE Debug: 360 5531 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_irscan dm8148.jrc 0x3F -endstate RUN/IDLE Debug: 361 5531 command.c:151 script_debug(): command - irscan ocd_irscan dm8148.jrc 0x3F -endstate RUN/IDLE Debug: 363 5533 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_runtest 10 Debug: 364 5533 command.c:151 script_debug(): command - runtest ocd_runtest 10 Info : 366 5536 tcl.c:674 jtag_tap_handle_event(): JTAG tap: dm8148.dap enabled Debug: 367 5536 core.c:329 jtag_call_event_callbacks(): jtag event: TAP enabled Debug: 368 5536 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu cget -chain-position Debug: 369 5536 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu cget -chain-position Debug: 370 5536 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled dm8148.dap Debug: 371 5536 command.c:151 script_debug(): command - ocd_jtag ocd_jtag tapisenabled dm8148.dap Debug: 372 5536 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu arp_examine Debug: 373 5536 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu arp_examine Debug: 374 5536 cortex_a.c:91 cortex_a8_init_debug_access(): Debug: 375 5541 adi_v5_jtag.c:274 jtagdp_transaction_endcheck(): jtag-dp: CTRL/STAT error, 0x20 Debug: 376 5541 arm_adi_v5.c:987 ahbap_debugport_init(): User : 377 5549 cortex_a.c:104 cortex_a8_init_debug_access(): Locking debug access failed on first, but succeeded on second try. Debug: 378 5554 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu invoke-event reset-assert-pre Debug: 379 5554 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu invoke-event reset-assert-pre Debug: 380 5554 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu cget -chain-position Debug: 381 5554 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu cget -chain-position Debug: 382 5554 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled dm8148.dap Debug: 383 5554 command.c:151 script_debug(): command - ocd_jtag ocd_jtag tapisenabled dm8148.dap Debug: 384 5554 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu arp_reset assert 0 Debug: 385 5554 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu arp_reset assert 0 Debug: 386 5554 cortex_a.c:1538 cortex_a8_assert_reset(): Debug: 387 5554 target.c:3681 target_handle_event(): target: (0) dm8148.cpu (cortex_a8) event: 11 (reset-assert) action: dm8148.cpu mww phys 0x481800A0 0x1 Debug: 388 5554 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu mww phys 0x481800A0 0x1 Debug: 389 5554 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu mww phys 0x481800A0 0x1 Debug: 390 5554 cortex_a.c:1830 cortex_a8_write_phys_memory(): Writing memory to real address 0x481800a0; size 4; count 1 Debug: 391 5556 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu invoke-event reset-assert-post Debug: 392 5556 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu invoke-event reset-assert-post Debug: 393 5556 target.c:3681 target_handle_event(): target: (0) dm8148.cpu (cortex_a8) event: 12 (reset-assert-post) action: omap3_dbginit dm8148.cpu Debug: 394 5556 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu cortex_a8 dbginit Debug: 395 5556 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu cortex_a8 dbginit Debug: 397 5556 cortex_a.c:91 cortex_a8_init_debug_access(): Debug: 398 5569 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu invoke-event reset-deassert-pre Debug: 399 5569 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu invoke-event reset-deassert-pre Debug: 400 5569 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu cget -chain-position Debug: 401 5569 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu cget -chain-position Debug: 402 5569 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled dm8148.dap Debug: 403 5569 command.c:151 script_debug(): command - ocd_jtag ocd_jtag tapisenabled dm8148.dap Debug: 404 5569 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu arp_reset deassert 0 Debug: 405 5569 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu arp_reset deassert 0 Debug: 406 5569 cortex_a.c:1567 cortex_a8_deassert_reset(): Debug: 407 5573 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu invoke-event reset-deassert-post Debug: 408 5573 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu invoke-event reset-deassert-post Debug: 409 5573 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_dm8148.cpu invoke-event reset-end Debug: 410 5573 command.c:151 script_debug(): command - ocd_dm8148.cpu ocd_dm8148.cpu invoke-event reset-end Debug: 411 7449 command.c:151 script_debug(): command - ocd_command ocd_command type ocd_halt Debug: 412 7449 command.c:151 script_debug(): command - halt ocd_halt Debug: 414 7451 target.c:2206 handle_halt_command(): - Error: 415 8457 cortex_a.c:856 cortex_a8_halt(): Timeout waiting for halt Debug: 416 8457 command.c:638 run_command(): Command failed with error code -4 User : 417 8457 command.c:679 command_run_line(): in procedure 'halt' Debug: 418 8457 log.c:437 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (1017). This may cause trouble with GDB connections. Can anyone suggest what could be wrong or provide pointers? (I did search for similar issues before posting but nothing I saw is either applicable or solves my issue). Thank you in advance. Kind Regards -- Delio Brignoli AudioScience Inc ------------------------------------------- DM8148 configuration file adapter_khz 0 #jtag_rclk 100 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME dm8148 } source [find target/icepick.cfg] proc icepick_d_tapenable {jrc port} { # NOTE: it's important not to enter RUN/IDLE state until # done sending these instructions and data to the ICEpick. # And never to enter RESET, which will disable the TAPs. # select router irscan $jrc 7 -endstate IRPAUSE drscan $jrc 8 0x89 -endstate DRPAUSE # set ip control irscan $jrc 2 -endstate IRPAUSE drscan $jrc 32 [expr 0xa0002108 | (($port & 0xF) << 24)] -endstate DRPAUSE drscan $jrc 32 0xe0002008 -endstate DRPAUSE irscan $jrc 0x3F -endstate RUN/IDLE runtest 10 } proc icepick_d_tapenable_bdi {jrc port} { # NOTE: it's important not to enter RUN/IDLE state until # done sending these instructions and data to the ICEpick. # And never to enter RESET, which will disable the TAPs. # select router irscan $jrc 7 -endstate IRPAUSE drscan $jrc 8 0x89 -endstate DRPAUSE # set ip control irscan $jrc 2 -endstate IRPAUSE # Keep powered drscan $jrc 32 81000080 -endstate DRPAUSE drscan $jrc 32 [expr 0xa0002008 | (($port & 0xF) << 24)] -endstate DRPAUSE drscan $jrc 32 0xe0002008 -endstate DRPAUSE drscan $jrc 32 [expr 0xa0002108 | (($port & 0xF) << 24)] -endstate DRPAUSE irscan $jrc 0x3F -endstate RUN/IDLE runtest 10 } # # A8 DAP # if { [info exists DAP_TAPID ] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x4b6b902f } jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_DAP_TAPID -disable jtag configure $_CHIPNAME.dap -event tap-enable \ "icepick_d_tapenable_bdi $_CHIPNAME.jrc 12" # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan if { [info exists JRC_TAPID ] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x3b8f202f } jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ -expected-id $_JRC_TAPID # Required by ICEpick to power-up the debug domain jtag configure $_CHIPNAME.jrc -event post-reset "runtest 1000" # # GDB target: Cortex-A8, using DAP # set _TARGETNAME $_CHIPNAME.cpu set _coreid 0 # DGBBASE is some magic number you have to know to make it all work, the DAP's value is wrong set _dbgbase 0x80001000 echo "Using dbgbase = [format 0x%x $_dbgbase]" target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \ -coreid 0 -dbgbase $_dbgbase # SRAM: 56KiB at 0x4030.0000 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 # Once the JRC is up, enable our TAPs jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset # ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. set PRM_RSTCTRL 0x481800A0 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" # Soft breakpoints don't currently work due to broken cache handling gdb_breakpoint_override hard reset_config trst_only #reset_config trst_only trst_push_pull # Disable verify_ircapture for openocd 0.6.0 #verify_ircapture disable proc omap3_dbginit {target} { # General Cortex A8 debug initialisation $target cortex_a8 dbginit } $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME" ------------------------------------------------------------------------------ Ridiculously easy VDI. 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