Dear List,
I'm working with iMX25. Happily I noticed that Erik Ahlén added support for
iMX35 NFC and that it is identical to the one in iMX25.
The attached patch adds support for iMX25 based on Erik's work. It defines the
CCM.RCSR register which is in different address in iMX25.
I also noticed that SPAS register (oob size) is left wrong after reset with
respect to 2KiB page NAND chip. I got ECC errors after 'reset halt'. I hard
wired it to 64B. I'm not really happy with that. Does anyone have a good
suggestion how and where to resolve right size?
Report of erased blocks in tcl.c was confusing, I would think.
Comments, please.
--
Timo
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index 50e4123..3017019 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -39,6 +39,7 @@
* !! all function only tested with 2k page nand device; mxc_write_page
* writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
* !! oob must be be used due to NFS bug
+ * !! oob must be 64 bytes per 2KiB page
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
@@ -48,9 +49,12 @@
#include "mxc.h"
#include <target/target.h>
+#define OOB_SIZE 64
+
#define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
mxc_nf_info->mxc_version == MXC_VERSION_MX31)
-#define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX35)
+#define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
+ mxc_nf_info->mxc_version == MXC_VERSION_MX35)
/* This permits to print (in LOG_INFO) how much bytes
* has been written after a page read or write.
@@ -95,14 +99,18 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
nand->controller_priv = mxc_nf_info;
if (CMD_ARGC < 4) {
- LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
+ LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
return ERROR_FAIL;
}
/*
* check board type
*/
- if (strcmp(CMD_ARGV[2], "mx27") == 0) {
+ if (strcmp(CMD_ARGV[2], "mx25") == 0) {
+ mxc_nf_info->mxc_version = MXC_VERSION_MX25;
+ mxc_nf_info->mxc_base_addr = 0xBB000000;
+ mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
+ } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
mxc_nf_info->mxc_version = MXC_VERSION_MX27;
mxc_nf_info->mxc_base_addr = 0xD8000000;
mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
@@ -230,6 +238,10 @@ static int mxc_init(struct nand_device *nand)
SREG = MX3_PCSR;
SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
SEL_FMS = MX3_PCSR_NF_FMS;
+ } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
+ SREG = MX25_RCSR;
+ SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
+ SEL_FMS = MX25_RCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
SREG = MX35_RCSR;
SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
@@ -723,6 +735,7 @@ static int initialize_nf_controller(struct nand_device *nand)
LOG_DEBUG("MXC_NF : work without ECC mode");
}
if (nfc_is_v2()) {
+ target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
if (nand->page_size) {
uint16_t pages_per_block = nand->erase_size / nand->page_size;
work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
diff --git a/src/flash/nand/mxc.h b/src/flash/nand/mxc.h
index b3a46b3..570ecba 100644
--- a/src/flash/nand/mxc.h
+++ b/src/flash/nand/mxc.h
@@ -37,7 +37,8 @@
#define MXC_NF_BUFCFG (mxc_nf_info->mxc_regs_addr + 0x0a)
#define MXC_NF_ECCSTATUS (mxc_nf_info->mxc_regs_addr + 0x0c)
#define MXC_NF_ECCMAINPOS (mxc_nf_info->mxc_regs_addr + 0x0e)
-#define MXC_NF_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
+#define MXC_NF_V1_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
+#define MXC_NF_V2_SPAS (mxc_nf_info->mxc_regs_addr + 0x10)
#define MXC_NF_FWP (mxc_nf_info->mxc_regs_addr + 0x12)
#define MXC_NF_V1_UNLOCKSTART (mxc_nf_info->mxc_regs_addr + 0x14)
#define MXC_NF_V1_UNLOCKEND (mxc_nf_info->mxc_regs_addr + 0x16)
@@ -116,6 +117,10 @@
#define MX2_FMCR 0x10027814
#define MX2_FMCR_NF_16BIT_SEL (1<<4)
#define MX2_FMCR_NF_FMS (1<<5)
+#define MX25_RCSR 0x53f80018
+#define MX25_RCSR_NF_16BIT_SEL (1<<14)
+#define MX25_RCSR_NF_FMS (1<<8)
+#define MX25_RCSR_NF_4K (1<<9)
#define MX3_PCSR 0x53f8000c
#define MX3_PCSR_NF_16BIT_SEL (1<<31)
#define MX3_PCSR_NF_FMS (1<<30)
@@ -126,8 +131,9 @@
enum mxc_version {
MXC_VERSION_UKWN = 0,
- MXC_VERSION_MX27 = 1,
- MXC_VERSION_MX31 = 2,
+ MXC_VERSION_MX25 = 1,
+ MXC_VERSION_MX27 = 2,
+ MXC_VERSION_MX31 = 3,
MXC_VERSION_MX35 = 4
};
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index c6ea3f3..53a3786 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -196,7 +196,7 @@ COMMAND_HANDLER(handle_nand_erase_command)
{
command_print(CMD_CTX, "erased blocks %lu to %lu "
"on NAND flash device #%s '%s'",
- offset, offset + length,
+ offset, offset + length - 1,
CMD_ARGV[0], p->device->name);
}
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