This is an automated email from Gerrit.
Timo Ketola (t...@exertus.fi) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/383
-- gerrit
commit 5da5a40b3846b3c76a160e76b47ad51f751dfe66
Author: Timo Ketola <t...@exertus.fi>
Date: Tue Jan 17 10:36:02 2012 +0200
i.MX25: Add support for i.MX25 NAND Flash Controller
This patch is based on Erik Ahlén's work on i.MX35 NFC support. Basically
it redefines the CCM.RCSR register which is in a different address in i.MX25.
Change-Id: Ia6faf9cb5efae5e564b72ef9a9b7c7f8bfde3ce0
Signed-off-by: Timo Ketola <t...@exertus.fi>
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index 50e4123..b6694ca 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -50,7 +50,8 @@
#define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
mxc_nf_info->mxc_version ==
MXC_VERSION_MX31)
-#define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX35)
+#define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
+ mxc_nf_info->mxc_version ==
MXC_VERSION_MX35)
/* This permits to print (in LOG_INFO) how much bytes
* has been written after a page read or write.
@@ -95,14 +96,18 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
nand->controller_priv = mxc_nf_info;
if (CMD_ARGC < 4) {
- LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35
noecc|hwecc [biswap]\"");
+ LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35
noecc|hwecc [biswap]\"");
return ERROR_FAIL;
}
/*
* check board type
*/
- if (strcmp(CMD_ARGV[2], "mx27") == 0) {
+ if (strcmp(CMD_ARGV[2], "mx25") == 0) {
+ mxc_nf_info->mxc_version = MXC_VERSION_MX25;
+ mxc_nf_info->mxc_base_addr = 0xBB000000;
+ mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr +
0x1E00;
+ } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
mxc_nf_info->mxc_version = MXC_VERSION_MX27;
mxc_nf_info->mxc_base_addr = 0xD8000000;
mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr +
0x0E00;
@@ -230,6 +235,10 @@ static int mxc_init(struct nand_device *nand)
SREG = MX3_PCSR;
SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
SEL_FMS = MX3_PCSR_NF_FMS;
+ } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
+ SREG = MX25_RCSR;
+ SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
+ SEL_FMS = MX25_RCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
SREG = MX35_RCSR;
SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
diff --git a/src/flash/nand/mxc.h b/src/flash/nand/mxc.h
index b3a46b3..570ecba 100644
--- a/src/flash/nand/mxc.h
+++ b/src/flash/nand/mxc.h
@@ -37,7 +37,8 @@
#define MXC_NF_BUFCFG
(mxc_nf_info->mxc_regs_addr + 0x0a)
#define MXC_NF_ECCSTATUS
(mxc_nf_info->mxc_regs_addr + 0x0c)
#define MXC_NF_ECCMAINPOS
(mxc_nf_info->mxc_regs_addr + 0x0e)
-#define MXC_NF_ECCSPAREPOS
(mxc_nf_info->mxc_regs_addr + 0x10)
+#define MXC_NF_V1_ECCSPAREPOS
(mxc_nf_info->mxc_regs_addr + 0x10)
+#define MXC_NF_V2_SPAS
(mxc_nf_info->mxc_regs_addr + 0x10)
#define MXC_NF_FWP
(mxc_nf_info->mxc_regs_addr + 0x12)
#define MXC_NF_V1_UNLOCKSTART
(mxc_nf_info->mxc_regs_addr + 0x14)
#define MXC_NF_V1_UNLOCKEND
(mxc_nf_info->mxc_regs_addr + 0x16)
@@ -116,6 +117,10 @@
#define MX2_FMCR
0x10027814
#define MX2_FMCR_NF_16BIT_SEL (1<<4)
#define MX2_FMCR_NF_FMS (1<<5)
+#define MX25_RCSR
0x53f80018
+#define MX25_RCSR_NF_16BIT_SEL (1<<14)
+#define MX25_RCSR_NF_FMS (1<<8)
+#define MX25_RCSR_NF_4K (1<<9)
#define MX3_PCSR
0x53f8000c
#define MX3_PCSR_NF_16BIT_SEL (1<<31)
#define MX3_PCSR_NF_FMS (1<<30)
@@ -126,8 +131,9 @@
enum mxc_version {
MXC_VERSION_UKWN = 0,
- MXC_VERSION_MX27 = 1,
- MXC_VERSION_MX31 = 2,
+ MXC_VERSION_MX25 = 1,
+ MXC_VERSION_MX27 = 2,
+ MXC_VERSION_MX31 = 3,
MXC_VERSION_MX35 = 4
};
--
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