Hello, did anybody program the STM32L1 via /src/flash/nor/stm32lx.c and the half_page algorithm successfully?
(github)stlink loads the same code as /src/flash/nor/stm32lx.c:stm32lx_flash_write_code_16[] but as soon as the code is executed, things go astray. The similar mechanisme for the F1 works. The STM32L errata CD00278726.pdf tells about problems > 2.1.3 Undefined instruction exception during IAP and suggests as a workaround: > Before branching to the RAM, the following procedure must be followed: > The vector table and all exception and interrupt handlers that might be > triggered must be copied into the RAM memory. The vector table offset must > be updated in the SCB_VTOR register of the Cortex-M3. The amount of RAM > memory needed can be minimized by disabling all interrupts during the IAP > execution. This can be done with the void __disable_irq(void) function > from the CMSIS library. Similarly, the Clock Security System (CSS) can be > disabled to prevent any NMI from occurring. However, it is mandatory to > remap at least the Cortex M3's fault handlers. Does this errata apply for the stm32lx_flash_write_code_16 code? Thanks -- Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- ------------------------------------------------------------------------------ Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
