Which EJTAG Control Register Fields must be set so that a processor will enter
the debug
mode?
I tried the following fields of the EJTAG Control Register
PrAcc( bit 18)
ProbEn( bit 15)
ProbTrap( bit 14)
and
EjtagBrk( bit 12)
but without success.
I used a code like this
...
set_instr(INSTR_CONTROL);//we want to work with EJTAG Control Register
WriteDataToDataRegister(PrAcc | ProbEn | ProbTrap | EjtagBrk );
Results=ReadDataFromDataRegister();
...
..
and according EJTAG specification, if CPU entered Debug mode,
DM(bit3) of EJTAG Control Register should be set to 1.
But when I check Results variable, I can see EjtagBrk( bit 12) is set to 1, but
DM(bit3) is still
zero.
Can anyone help please?
.
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