This is an automated email from Gerrit.
Mathias Küster (kes...@freenet.de) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/514
-- gerrit
commit f6d908acfae5af610efc66518fa2b57345a3f318
Author: Mathias K <kes...@freenet.de>
Date: Tue Mar 13 15:26:11 2012 +0100
armv7m: add fp registers
This patch add the fp registers to the armv7m register set.
Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kes...@freenet.de>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 258653e..f0e1a24 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -128,6 +128,40 @@ static const struct {
{ ARMV7M_BASEPRI, "basepri", 8 },
{ ARMV7M_FAULTMASK, "faultmask", 1 },
{ ARMV7M_CONTROL, "control", 2 },
+
+ { ARMV7M_FPSCR, "fpscr", 32 },
+ { ARMV7M_S0, "s0", 32 },
+ { ARMV7M_S1, "s1", 32 },
+ { ARMV7M_S2, "s2", 32 },
+ { ARMV7M_S3, "s3", 32 },
+ { ARMV7M_S4, "s4", 32 },
+ { ARMV7M_S5, "s5", 32 },
+ { ARMV7M_S6, "s6", 32 },
+ { ARMV7M_S7, "s7", 32 },
+ { ARMV7M_S8, "s8", 32 },
+ { ARMV7M_S9, "s9", 32 },
+ { ARMV7M_S10, "s10", 32 },
+ { ARMV7M_S11, "s11", 32 },
+ { ARMV7M_S12, "s12", 32 },
+ { ARMV7M_S13, "s13", 32 },
+ { ARMV7M_S14, "s14", 32 },
+ { ARMV7M_S15, "s15", 32 },
+ { ARMV7M_S16, "s16", 32 },
+ { ARMV7M_S17, "s17", 32 },
+ { ARMV7M_S18, "s18", 32 },
+ { ARMV7M_S19, "s19", 32 },
+ { ARMV7M_S20, "s20", 32 },
+ { ARMV7M_S21, "s21", 32 },
+ { ARMV7M_S22, "s22", 32 },
+ { ARMV7M_S23, "s23", 32 },
+ { ARMV7M_S24, "s24", 32 },
+ { ARMV7M_S25, "s25", 32 },
+ { ARMV7M_S26, "s26", 32 },
+ { ARMV7M_S27, "s27", 32 },
+ { ARMV7M_S28, "s28", 32 },
+ { ARMV7M_S29, "s29", 32 },
+ { ARMV7M_S30, "s30", 32 },
+ { ARMV7M_S31, "s31", 32 },
};
#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index cee2b60..5c10fec 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -62,7 +62,7 @@ char *armv7m_exception_string(int number);
/* offsets into armv7m core register cache */
enum {
/* for convenience, the first set of indices match
- * the Cortex-M3 DCRSR selectors
+ * the Cortex-M3/-M4 DCRSR selectors
*/
ARMV7M_R0,
ARMV7M_R1,
@@ -93,6 +93,41 @@ enum {
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,
ARMV7M_CONTROL,
+
+ /* Floating-point registers */
+ ARMV7M_FPSCR = 33,
+ ARMV7M_S0 = 64,
+ ARMV7M_S1,
+ ARMV7M_S2,
+ ARMV7M_S3,
+ ARMV7M_S4,
+ ARMV7M_S5,
+ ARMV7M_S6,
+ ARMV7M_S7,
+ ARMV7M_S8,
+ ARMV7M_S9,
+ ARMV7M_S10,
+ ARMV7M_S11,
+ ARMV7M_S12,
+ ARMV7M_S13,
+ ARMV7M_S14,
+ ARMV7M_S15,
+ ARMV7M_S16,
+ ARMV7M_S17,
+ ARMV7M_S18,
+ ARMV7M_S19,
+ ARMV7M_S20,
+ ARMV7M_S21,
+ ARMV7M_S22,
+ ARMV7M_S23,
+ ARMV7M_S24,
+ ARMV7M_S25,
+ ARMV7M_S26,
+ ARMV7M_S27,
+ ARMV7M_S28,
+ ARMV7M_S29,
+ ARMV7M_S30,
+ ARMV7M_S31
};
#define ARMV7M_COMMON_MAGIC 0x2A452A45
@@ -140,7 +175,7 @@ struct armv7m_algorithm {
enum armv7m_mode core_mode;
- uint32_t context[ARMV7M_CONTROL + 1]; /* ARMV7M_NUM_REGS */
+ uint32_t context[ARMV7M_S31 + 1]; /* ARMV7M_NUM_REGS */
};
struct armv7m_core_reg {
--
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