On Wed, Mar 28, 2012 at 04:54:00PM +0200, Javier Martin wrote: > According to p.82 of the datasheet, the erase region information > for the S29NS512P is configured as follows (16 bit addresses): > > Address Data Description > 2Dh 0x01FFh Number of sectors (lower byte) > 2Eh 0x0000h Number of sectors (upper byte) > 2Fh 0x0000h Density of bytes (lower byte) > 30h 0x0002h Density of bytes (upper byte) > > However, as stated by CFI standard one should expect that > the Number of sectors, which in this NOR spans more than 8 bits, > should be splitted as follows > > Address Data Description > 2Dh 0x00FFh Number of sectors (lower byte) > 2Eh 0x0001h Number of sectors (upper byte) > > To address this special behavior of 29NS512P I've prepared > the following RFC which has been tested in a Zylin ZY1000 > attached to a DM3730 custom board.
I don't think it is a good idea to clutter the CFI code to handle non-conforming behaviour of a single device. Unless there are lots of chips with similar problems, I think this should be addressed by fixup code outside the CFI code (eg. by adding the flash to the non-CFI tables). cu Michael ------------------------------------------------------------------------------ This SF email is sponsosred by: Try Windows Azure free for 90 days Click Here http://p.sf.net/sfu/sfd2d-msazure _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
