Hello!
I curently experience a pretty strange situation on a new ARM11 MPcore
board I am working on...
The board is using a Cavium CNS3420 SoC. I have made a custom OpenOCD
config based partially on Scott Shu's blog entry:
http://scottshulinux.blogspot.de/2011_03_01_archive.html
(openocd-cnx.cfg)
and some more initializations for the custom board I am working on -
like proper DDR config etc.
The first strange thing I am seeing should be pretty unrelated to extra
configs as I can also see this on the CNS3420 reference board: I can not
halt the CPU core.
After board switch-on U-Boot will come up and I can successfully attach
OpenOCD through the JTAG - the taps are found
Info : JTAG tap: arm11.cpu0 tap/device found: 0x07b37477 (mfg: 0x23b,
part: 0x7b37, ver: 0x0)
Info : JTAG tap: arm11.cpu1 tap/device found: 0x07b37477 (mfg: 0x23b,
part: 0x7b37, ver: 0x0)
Info : found ARM11 MPCore
If I then issue an OpenOCD "halt" command U-Boot will still be
responsive on the serial interface.
How is that? Shouldn't it *halt* the core?
My custom board I have to bring-up does not have pre-programmed flash
chips so I have to rely on being able to download the initial U-Boot
code to RAM and execute it from there.
I have written the necessary init sequence to get PLLs and the DDR
controller out of reset and can successfully write an image through JTAG
into the DDR RAM - I can after writing read back the image and it is
correct.
But a "resume" from the load address (here it is by default 0x00) does
not start U-Boot. *Sometimes* (roughly one out of a felt 100 times)
U-Boot either suddenly starts to execute on its own or it starts after a
subsequent new reset and board init.
This is pretty strange :(
And especially this is too unreliable for me to start actual development...
My current theory is that OpenOCD might communicate with the wrong core?
The CNS3420 is a SMP dual core CPU. After power on reset core0 takes
control and starts to execute from 0x00.
Assuming OpenOCD would go through core1 instead or core0 som eof my
above observations could probably explained.
But I have too little knowledge about ARM11 MPcore...
I have attached my current OpenOCD config if someone has a minute to
look over it...
Any idea how to overcome this situation would be really appreciated
since OpenOCD is at the moment my only choice to bring up the board. If
this results in a working CPU and board config for the CNS3420 I will of
course contribute this to OpenOCD if there is interest.
Cheers
nils
--
kernel concepts GmbH Tel: +49-271-771091-12
Sieghuetter Hauptweg 48
D-57072 Siegen Mob: +49-176-21024535
http://www.kernelconcepts.de
# source [find interface/olimex-arm-usb-ocd.cfg]
source [find interface/openocd-usb.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cns3000
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0x07B37477
}
if { [info exists BSTAPID ] } {
set _BSTAPID $BSTAPID
} else {
# force an error till we get a good number
set _BSTAPID 0xffffffff
}
reset_config trst_and_srst
jtag_ntrst_delay 100
jtag_nsrst_delay 100
jtag_khz 3000
jtag newtap arm11 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
$_CPUTAPID
jtag newtap arm11 cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
$_CPUTAPID
target create arm11.cpu arm11 -chain-position arm11.cpu -endian $_ENDIAN
-variant arm11
flash bank cnx.flash cfi 0x10000000 0x800000 2 2 arm11.cpu
proc gpio_init { } {
# Set all to alt func except GPIOA[28,23]
mww 0x76000014 0xEF7FFFFF
# Set all to alt func except GPIOB[31,30]
mww 0x76000018 0x3FFFFFFF
# Set GPIOA[28,23] to output (LED)
mww 0x74000008 0x10800000
# Set GPIOB[31,30] to output (LED)
mww 0x74800008 0xC0000000
# Set GPIOA[28,23] to 1 (LED)
mww 0x74000000 0x10800000
# Set GPIOB[31,30] to 1 (LED)
mww 0x74800000 0xC0000000
}
proc gpio_blink { } {
# LEDs are low active
# A off
mww 0x74000000 0x10800000
# B off
mww 0x74800000 0xC0000000
mww 0x74000000 0x00800000
sleep 500
mww 0x74000000 0x10000000
sleep 500
mww 0x74000000 0x10800000
mww 0x74800000 0x80000000
sleep 500
mww 0x74800000 0x40000000
sleep 500
mww 0x74800000 0xC0000000
sleep 500
}
proc cns3xxx_init { } {
halt 0
wait_halt
# DLL initialization
mww 0x72000400 0x00000000
mww 0x72000408 0x00001410
mww 0x7200040C 0x00000006
mww 0x72000410 0x00000000
mww 0x72000414 0x00000000
mww 0x72000418 0x00000000
mww 0x7200041C 0x00000000
mww 0x72000420 0x00000000
mww 0x72000424 0x00000018
# set ctrl_dll_on
mww 0x72000404 0x00000001
# set ctrl_start
mww 0x72000404 0x00000003
# ZQ initialization
mww 0x72000428 0x0000E550
sleep 1
mww 0x72000428 0x0000E554
sleep 1
mww 0x72000428 0x0000E556
sleep 1
mww 0x72000428 0x0000E554
sleep 1
# setting for DDR2 Controller
mww 0x72000430 0x00000002
mww 0x72000014 0x0000000C
mww 0x7200001C 0x00000002
# For MCLK=400MHZ settings
mww 0x72000020 0x00000012
mww 0x72000024 0x00000018
mww 0x72000028 0x00000206
mww 0x7200002C 0x00002433
mww 0x72000030 0x00000206
mww 0x72000034 0x00000004
mww 0x72000038 0x00000006
mww 0x7200003C 0x00000003
mww 0x72000054 0x00000b14
mww 0x72000040 0x00000003
mww 0x72000044 0x000000C8
mww 0x72000048 0x000000C8
mww 0x7200000C 0x0001401a
mww 0x72000010 0x00000C30
mww 0x7200004C 0x00000574
mww 0x72000200 0x000000FF
mww 0x72000008 0x000C0000
mww 0x72000008 0x00000000
mww 0x72000008 0x000A0000
mww 0x72000008 0x000B0000
mww 0x72000008 0x00090040
mww 0x72000008 0x00080B62
mww 0x72000008 0x00000000
mww 0x72000008 0x00040000
mww 0x72000008 0x00040000
mww 0x72000008 0x00080A62
mww 0x72000008 0x000903C0
mww 0x72000008 0x00090040
mww 0x72000004 0x00000000
mww 0x76000000 0x00000001
mww 0x7700001C 0x00000000
mww 0x77000000 0xFFFFFFFF
mww 0x77000004 0xFFFFFFFF
mww 0x77000004 0xFFFFFFFD
mww 0x77000004 0xFFFFFFFF
#mww 0x76000014 0xFFFFFF0C
#mww 0x76000018 0xFFFFFFFF
gpio_init
mww 0x77000020 0x00469A59
}
proc cns3xxx_uinit { } {
halt 0
wait_halt
# DLL initialization
mww 0x72000400 0x00000000
mww 0x72000408 0x00001410
mww 0x7200040C 0x00000006
mww 0x72000410 0x00000000
mww 0x72000414 0x00000000
mww 0x72000418 0x00000000
mww 0x7200041C 0x00000000
mww 0x72000420 0x00000000
mww 0x72000424 0x00000000
# set ctrl_dll_on
mww 0x72000404 0x00000001
# set ctrl_start
mww 0x72000404 0x00000003
# ZQ initialization
mww 0x72000428 0x0006E550
mww 0x72000428 0x0006E551
mww 0x72000428 0x0006E550
mww 0x72000428 0x0007E550
# setting for DDR2 Controller
mww 0x72000430 0x00000002
mww 0x72000014 0x0000000C
mww 0x7200001C 0x00000002
# For MCLK=400MHZ settings
mww 0x72000020 0x00000012
mww 0x72000024 0x00000018
mww 0x72000028 0x00000206
mww 0x7200002C 0x00002433
mww 0x72000030 0x00000206
mww 0x72000034 0x00000004
mww 0x72000038 0x00000006
mww 0x7200003C 0x00000003
mww 0x72000054 0x00000b14
mww 0x72000040 0x00000003
mww 0x72000044 0x000000C8
mww 0x72000048 0x000000C8
mww 0x7200000C 0x0001401a
mww 0x72000010 0x00000C30
mww 0x7200004C 0x00000574
mww 0x72000200 0x000000FF
mww 0x72000008 0x000C0000
mww 0x72000008 0x00000000
mww 0x72000008 0x000A0000
mww 0x72000008 0x000B0000
mww 0x72000008 0x00090040
mww 0x72000008 0x00080B62
mww 0x72000008 0x00000000
mww 0x72000008 0x00040000
mww 0x72000008 0x00040000
mww 0x72000008 0x00080A62
mww 0x72000008 0x000903C4
mww 0x72000008 0x00090044
mww 0x72000004 0x00000000
mww 0x76000000 0x00000001
mww 0x7700001C 0x00000000
mww 0x77000000 0xFFFFFFFF
mww 0x77000004 0xFFFFFFFF
mww 0x77000004 0xFFFFFFFD
mww 0x77000004 0xFFFFFFFF
# mww 0x76000014 0xFFFFFF0C # GPIO_A pin enable
# mww 0x76000018 0xFFFFFFFF # GPIO_B pin enable
gpio_init
# mww 0x77000020 0x00469A59
mww 0x77000020 0x0247DE59
}
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