Tim, This device has a JTAG security module (jsm) that must have the keys match before the Flash memory may be read. Currently the documentation for this module is available only under NDA.
Secondly, this device would behave more like the TMS470R1A384 support in OpenOCD plus the addition of the jsm than it would as a Luminary device (different development histories). Best Regards, John R Hall Hercules Software Applications Texas Instruments -----Original Message----- From: Tim Wescott [mailto:[email protected]] Sent: Tuesday, August 21, 2012 1:22 PM To: [email protected] Subject: [OpenOCD-devel] Troubles with SA470R1B1 (TMS470R1B1) I'm trying to work with a TI SA470R1B1 chip. This is -- as near as I can tell -- a high-temperature qualified version of the TMS470R1B1. So in theory what applies to the TMS470R1B1 should apply to the SA470R1B1. I've got many happy miles using OpenOCD with newer Cortex M3 parts (both TI/Luminary and ST), so I assume that my problems are specific either to this processor, or to the ARM7 core. I'm going to err on the side of too much detail here -- bear with me, and feel free to pick and choose what you look at. I'm mostly working under Ubuntu 10.04, with OpenOCD version 0.4.0, but I get the same errors under 12.04 and OpenOCD version 0.5.0. I'm using a cobbled-together set of config files, because the TMS470 doesn't appear in the "target" directory of either install. I'm including the pertinent config files at the end of the message (I assume this list does not support attachments). The hardware I'm using is an evaluation board from IAR which came with a Segger Jlink lite, which I was completely unable to make work. So for the moment I'm trying this with an Olimex JTAG tiny interface. When I start openocd, I get a normal-looking message: > tim@servo:~/Documents/Customer/Technical/Software/codesourcery$ > openocd > Open On-Chip Debugger 0.4.0 (2010-10-08-15:42) Licensed under GNU GPL > v2 For bug reports, read > http://openocd.berlios.de/doc/doxygen/bugs.html > trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain > 1000 kHz > fast memory access is enabled > dcc downloads are enabled > 500 kHz > jtag_nsrst_delay: 100 > jtag_ntrst_delay: 100 > Info : clock speed 500 kHz > Info : JTAG tap: tms470r1b1m.cpu tap/device found: 0x3100e02f (mfg: > 0x017, part: 0x100e, ver: 0x3) > Info : Embedded ICE version 1 > Info : tms470r1b1m.cpu: hardware has 2 breakpoint/watchpoint units The first sign of trouble comes when I try to read memory: I use "mdw 0 8", and I get a warning that the target isn't halted. So, I halt the target and I get "Command handler execution failed", then a flood of messages: > Error: invalid mode value encountered 0 > Error: cpsr contains invalid mode value - communication failure Typing "reset halt" calms the flood, but when I try "mdw 0 8", instead of getting something flash-like I get all zeros. Trying "mdw 0xfffffe00 8" (which should be hard-mapped on this chip) also gets me all zeros. In fact, everything I've tried gets me all zeros. Plunging further in, I tried to write to flash with the command "flash write_image erase code/Debug/bob.elf", which gets me the messages: > auto erase enabled > Info : device_ident_reg = 0x00000000 > Warn : Cannot identify target as a TMS470 family. > Error: auto_probe failed -902 > > Info : device_ident_reg = 0x00000000 > Warn : Cannot identify target as a TMS470 family. > Error: auto_probe failed -902 > > wrote 0 bytes from file code/Debug/bob.elf in 0.023038s (0.000 kb/s) So, I'm lost. Clearly the device is reading back all zeros for any memory access, can't read memory at all when the processor is running, and for whatever reason doesn't like halting anywhere but at reset. What's causing the all-zeros problem is beyond me, and I don't even know if it's kosher to try reading memory on a running ARM7 core. So -- help? My openocd.cfg file reads: > # config file for the IAR SM470R1B1M-SK, with "J-link lite" > # I'm flying blind here, so if you find anything that seems screwy # > and you know a better way -- try it > > source [find interface/olimex-jtag-tiny.cfg] #source [find > interface/luminary.cfg] source [find tms470r1b1.cfg] #source [find > target/stellaris.cfg] > > # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use > F_JTAG = 1MHz jtag_khz 500 > > jtag_nsrst_delay 100 > jtag_ntrst_delay 100 the olimex-jtag-tiny.cfg file hasn't been changed, and the tms470r1b1.cfg file is one that I copied from a post which I believe came from this list three or four years ago: > # TI TMS470R1B1M Configuration > > if { [info exists CHIPNAME] } { > set _CHIPNAME $CHIPNAME > } else { > set _CHIPNAME tms470r1b1m > } > > if { [info exists ENDIAN] } { > set _ENDIAN $ENDIAN > } else { > set _ENDIAN big > } > > if { [info exists CPUTAPID ] } { > set _CPUTAPID $CPUTAPID > } else { > set _CPUTAPID 0x3100e02f > } > > > #TMS470 Reset config > reset_config trst_and_srst > > #jtag scan chain > jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf > -expected-id $_CPUTAPID > > # jtag speed > jtag_khz 1000 > > #jtag_nsrst_delay 200 > #jtag_ntrst_delay 200 > > set _TARGETNAME $_CHIPNAME.cpu > target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position > $_CHIPNAME.cpu -variant arm7tdmi > > #flash configuration > set _FLASHNAME $_CHIPNAME.flash > flash bank $_FLASHNAME tms470 0 0 0 0 $_TARGETNAME > > arm7_9 fast_memory_access enable > arm7_9 dcc_downloads enable > > $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 > -work-area-size 0x4000 -work-area-backup 0 -- Tim Wescott www.wescottdesign.com Control & Communications systems, circuit & software design. ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
