Hi,
I solved my problem by altering reset configuration according to this
description:
http://sourceforge.net/apps/trac/openocd/ticket/19
Regards,
Kuba
2012/9/7 Kuba Dorzak <jdor...@gmail.com>
> Hi Everybody,
>
> I have LPC2478 with an external SDRAM. I wrote a script which sets PLL and
> inits the SDRAM based on the ready board script
> embedded-artists_lpc2478-32.cfg. It works fine. Now I am working on LPC1788
> (Cortex-M3). I need to set PLL to 120 MHz and init SDRAM as well. I call
> the reset-init event which sets PLL but flashing fails. Here's my script:
>
> set CCLK 120000
>
> if { [info exists CHIPNAME] } {
> set _CHIPNAME $CHIPNAME
> } else {
> set _CHIPNAME lpc1788
> }
>
> if { [info exists ENDIAN] } {
> set _ENDIAN $ENDIAN
> } else {
> set _ENDIAN little
> }
>
> if { [info exists CCLK ] } {
> set _CCLK $CCLK
> } else {
> set _CCLK 120000
> }
>
> if { [info exists CPUTAPID ] } {
> set _CPUTAPID $CPUTAPID
> } else {
> set _CPUTAPID 0x4ba00477
> }
>
> #delays on reset lines
> adapter_nsrst_delay 500
> jtag_ntrst_delay 500
>
> reset_config trst_and_srst separate
> #reset_config trst_and_srst trst_pulls_srst
>
> jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
> #swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
>
> set _TARGETNAME $_CHIPNAME.cpu
> target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
> $_TARGETNAME
>
> # LPC1788 has 64kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
> # and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
> $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x10000
>
> # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock>
> [calc checksum]
> set _FLASHNAME $_CHIPNAME.flash
> flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 $_CCLK
> calc_checksum
>
> jtag_khz 20
>
> proc mamInit {} {
> mww 0x400FC000 0x0000403A ;# FLASHCFG = 16442;
> puts "mamInit() done"
> }
>
> proc configurePll {} {
> mww 0x400FC1A0 0x00000029 ;# SCS |= (1 << 5);
> sleep 2000 ;# while( ((SCS & (1 << 6)) == 0) );
>
> # mww 0x400fc10c 0x00000000 ;# CLKSRCSEL = 0;// select the Internal
> RC oscillator
> # mww 0x400fc080 0x00000000 ;# PLL0CON = 0; // disable PLL0
> # pllFeed() // feed sequence
> # mww 0x400fc08c 0x000000AA ;# PLL0FEED = PLLFEED_FIRST;
> # mww 0x400fc08c 0x00000055 ;# PLL0FEED = PLLFEED_SECOND;
>
> mww 0x400fc10c 0x00000001 ;# CLKSRCSEL = 1;// select the main osc
> as the sysclk and PLL0 clock source
>
> mww 0x400fc084 0x00000009 ;#PLL0CFG = PLL_MValue | (PLL_PValue <<
> 5);
> # pllFeed()
> mww 0x400FC08C 0x000000AA ;# PLL0FEED = PLLFEED_FIRST;
> mww 0x400FC08C 0x00000055 ;# PLL0FEED = PLLFEED_SECOND;
>
> mww 0x400FC080 0x00000001 ;# PLL0CON = 1;
> # pllFeed()
> mww 0x400FC08C 0x000000AA ;# PLL0FEED = PLLFEED_FIRST;
> mww 0x400FC08C 0x00000055 ;# PLL0FEED = PLLFEED_SECOND;
> sleep 1000
>
> mww 0x400FC104 0x00000001 ;# CCLKSEL = 1;
> mww 0x400FC100 0x00000000 ;# EMCCLKSEL = 0;
> mww 0x400FC1A8 0x00000001 ;# PCLKSEL = 1;
> mww 0x400FC108 0x00000000 ;# USBCLKSEL = 0;
> sleep 1000 ;# while( ((PLL0STAT & (1 << 10)) == 0) );
>
> mww 0x400FC104 0x00000101 ;# CCLKSEL = 1 | (1 << 8);
> jtag_khz 500
> puts "configurePll() done"
> }
>
> proc sdram_init {} {
> /* not yet */
> }
>
> $_TARGETNAME configure -event reset-start {
> # Back to the slow JTAG clock
> jtag_khz 20
> }
>
> $_TARGETNAME configure -event reset-init {
> mww 0x400FC040 0x01
> configurePll
> mamInit
> # sdram_init
> }
>
> And here's the output I got:
>
> Open On-Chip Debugger 0.5.0 (2011-12-03-08:57)
> Licensed under GNU GPL v2
> For bug reports, read
> http://openocd.berlios.de/doc/doxygen/bugs.html
> Info : only one transport option; autoselect 'jtag'
> adapter_nsrst_delay: 500
> jtag_ntrst_delay: 500
> trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
> 20 kHz
> Info : clock speed 20 kHz
> Info : JTAG tap: lpc1788.cpu tap/device found: 0x4ba00477 (mfg: 0x23b,
> part: 0xba00, ver: 0x4)
> Info : lpc1788.cpu: hardware has 6 breakpoints, 4 watchpoints
> Info : accepting 'gdb' connection from 3333
> Warn : acknowledgment received, but no packet pending
> undefined debug reason 6 - target needs reset
> cortex_m3 reset_config ['srst'|'sysresetreq'|'vectreset']
> ft2232_layout layout_name
> jtag arp_init-reset
> jtag_reset trst_active srst_active
> lpc1788.cpu arp_examine
> lpc1788.cpu arp_halt
> lpc1788.cpu arp_halt_gdb
> lpc1788.cpu arp_poll
> lpc1788.cpu arp_reset
> lpc1788.cpu arp_waitstate
> power_restore
> reset [run|halt|init]
> reset_config [none|trst_only|srst_only|trst_and_srst]
> [srst_pulls_trst|trst_pulls_srst|combined|separate]
> [srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain]
> [srst_push_pull|srst_open_drain]
> reset_nag ['enable'|'disable']
> soft_reset_halt
> srst_deasserted
> stacktrace
> in procedure 'reset'
> Error: Target not halted
> Error: failed erasing sectors 0 to 2
> Error: flash_erase returned -304
> Warn : WARNING! The target is already running. All changes GDB did to
> registers will be discarded! Waiting for target to halt.
>
> Any ideas? Does anyone successfully init PLL by OOCD and is able to flash
> the chip?
>
> Regards,
> Kuba
>
>
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