This is an automated email from Gerrit.
Gianluca Renzi (gianlucare...@eurekelettronica.it) just uploaded a new patch
set to Gerrit, which you can find at http://openocd.zylin.com/927
-- gerrit
commit e71c8e42e975719580e56e6242e23f9187621c52
Author: Gianluca Renzi <gianluca@gianlinux.(none)>
Date: Wed Oct 24 14:57:17 2012 +0200
- Added LPC1850 board and target configuration .cfg files
- Added a new SPI Flash Memory ID in the SPI driver table:
Winbond W25Q64CV 64Mbit/8Mbytes
Change-Id: I24ec9c48671cea198b836e1e0d9ba6efb0fef71b
Signed-off-by: Gianluca Renzi <gianlucare...@eurekelettronica.it>
diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c
index 7046edd..7b0abd3 100644
--- a/src/flash/nor/spi.c
+++ b/src/flash/nor/spi.c
@@ -66,5 +66,6 @@ struct flash_device flash_devices[] = {
FLASH_ID("mac 25l3205", 0xd8, 0xC7, 0x001620c2, 0x100, 0x10000,
0x400000),
FLASH_ID("mac 25l6405", 0xd8, 0xC7, 0x001720c2, 0x100, 0x10000,
0x800000),
FLASH_ID("win w25q32dw", 0xd8, 0xC7, 0x001660ef, 0x100, 0x10000,
0x400000),
+ FLASH_ID("win w25q64cv", 0xd8, 0xC7, 0x001740ef, 0x100, 0x10000,
0x800000),
FLASH_ID(NULL, 0, 0, 0, 0, 0,
0)
};
diff --git a/tcl/board/lpc1850_spifi_generic.cfg
b/tcl/board/lpc1850_spifi_generic.cfg
new file mode 100644
index 0000000..cea0753
--- /dev/null
+++ b/tcl/board/lpc1850_spifi_generic.cfg
@@ -0,0 +1,18 @@
+#
+# Generic LPC4350 board w/ SPIFI flash.
+# This config file is intended as an example of how to
+# use the lpcspifi flash driver, but it should be functional
+# for most LPC4350 boards utilizing SPIFI flash.
+
+set CHIPNAME lpc1850
+
+source [find target/lpc1850.cfg]
+
+#A large working area greatly reduces flash write times
+set _WORKAREASIZE 0x4000
+
+$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size
$_WORKAREASIZE
+
+#Configure the flash bank; 0x14000000 is the base address for
+#lpc43xx/lpc18xx family micros.
+flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
new file mode 100644
index 0000000..a4c7478
--- /dev/null
+++ b/tcl/target/lpc1850.cfg
@@ -0,0 +1,37 @@
+
+adapter_khz 500
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc1850
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+#
+# M3 JTAG mode TAP
+#
+if { [info exists M3_JTAG_TAPID] } {
+ set _M3_JTAG_TAPID $M3_JTAG_TAPID
+} else {
+ set _M3_JTAG_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_M3_JTAG_TAPID
+
+
+#jtag scan chain
+#if { [info exists CPUTAPID] } {
+# set _CPUTAPID $CPUTAPID
+#} else {
+# set _CPUTAPID 0x3ba00477
+#}
+#jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+
+set _TARGETNAME $_CHIPNAME.m3
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
--
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