This is an automated email from Gerrit. Spencer Oliver ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/967
-- gerrit commit 2fa32d7d1d6d614664338c56b93eb902395c9811 Author: Spencer Oliver <[email protected]> Date: Thu Nov 8 14:50:05 2012 +0000 armv7m: remove unused armv7m_regtype This simplifies the armv7m_core_reg structure ready for the move to using the generic struct arm_reg. Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964 Signed-off-by: Spencer Oliver <[email protected]> diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 1975b79..c6715d3 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -213,7 +213,6 @@ static int armv7m_read_core_reg(struct target *target, unsigned num) armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; retval = armv7m->load_core_reg_u32(target, - armv7m_core_reg->type, armv7m_core_reg->num, ®_value); buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value); @@ -236,7 +235,6 @@ static int armv7m_write_core_reg(struct target *target, unsigned num) reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; retval = armv7m->store_core_reg_u32(target, - armv7m_core_reg->type, armv7m_core_reg->num, reg_value); if (retval != ERROR_OK) { @@ -429,7 +427,7 @@ int armv7m_wait_algorithm(struct target *target, return ERROR_TARGET_TIMEOUT; } - armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); + armv7m->load_core_reg_u32(target, 15, &pc); if (exit_point && (pc != exit_point)) { LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32, pc, diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 4c2445b..d5006c2 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -43,12 +43,6 @@ extern struct reg armv7m_gdb_dummy_cpsr_reg; extern const int armv7m_psp_reg_map[]; extern const int armv7m_msp_reg_map[]; -enum armv7m_regtype { - ARMV7M_REGISTER_CORE_GP, - ARMV7M_REGISTER_CORE_SP, - ARMV7M_REGISTER_MEMMAP -}; - char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ @@ -168,10 +162,8 @@ struct armv7m_common { bool stlink; /* Direct processor core register read and writes */ - int (*load_core_reg_u32)(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t *value); - int (*store_core_reg_u32)(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value); + int (*load_core_reg_u32)(struct target *target, uint32_t num, uint32_t *value); + int (*store_core_reg_u32)(struct target *target, uint32_t num, uint32_t value); /* register cache to processor synchronization */ int (*read_core_reg)(struct target *target, unsigned num); @@ -204,7 +196,6 @@ struct armv7m_algorithm { struct armv7m_core_reg { uint32_t num; - enum armv7m_regtype type; struct target *target; struct armv7m_common *armv7m_common; }; diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 54e2a8e..da258bd 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -61,7 +61,7 @@ /* forward declarations */ static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value); + uint32_t num, uint32_t value); static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, uint32_t *value, int regnum) @@ -446,7 +446,7 @@ static int cortex_m3_debug_entry(struct target *target) /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ if (xPSR & 0xf00) { r->dirty = r->valid; - cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR & ~0xff); + cortex_m3_store_core_reg_u32(target, 16, xPSR & ~0xff); } /* Are we in an exception handler */ @@ -1464,7 +1464,7 @@ void cortex_m3_enable_watchpoints(struct target *target) } static int cortex_m3_load_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t *value) + uint32_t num, uint32_t *value) { int retval; struct armv7m_common *armv7m = target_to_armv7m(target); @@ -1525,7 +1525,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target, } static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value) + uint32_t num, uint32_t value) { int retval; uint32_t reg; diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c index e44fe7a..2af6e06 100644 --- a/src/target/stm32_stlink.c +++ b/src/target/stm32_stlink.c @@ -47,7 +47,6 @@ static inline struct stlink_interface_s *target_to_stlink(struct target *target) } static int stm32_stlink_load_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t *value) { int retval; @@ -144,7 +143,6 @@ static int stm32_stlink_load_core_reg_u32(struct target *target, } static int stm32_stlink_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; -- ------------------------------------------------------------------------------ Everyone hates slow websites. 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