This is an automated email from Gerrit. Jared Boone ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1000
-- gerrit commit 053a5b509dcbc26c180b32620b7af987daa8b7bd Author: Jared Boone <[email protected]> Date: Sun Dec 2 19:16:44 2012 -0800 flash: NXP LPC11Uxx flash implementation Extended the LPC17xx flash implementation in lpc2000.c to support LPC11Uxx devices. Code is tested with ST-Link/V2 connected to NXP LPCXpresso LPC11U14 rev A board, bypassing (proprietary?) LPC-Link and using SWD directly to target. Added target configuration files for the ST-Link/V2 -> LPC11U14 scenario. Change-Id: I5dc785cc6859a7f53a8275b7df2723d44c8ed15b Signed-off-by: Jared Boone <[email protected]> diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 06f3ec4..64591d0 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -4,6 +4,8 @@ * * * LPC1700 support Copyright (C) 2009 by Audrius Urmanavicius * * [email protected] * + * LPC11Uxx support Copyright (C) 2012 by Jared Boone, ShareBrained * + * Technology, [email protected] * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -33,7 +35,7 @@ /** * @file - * flash programming support for NXP LPC17xx and LPC2xxx devices. + * flash programming support for NXP LPC11Uxx, LPC17xx and LPC2xxx devices. * * @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will * rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz). @@ -58,12 +60,16 @@ * lpc1700: * - 175x * - 176x (tested with LPC1768) + * + * lpc11u: + * - 11Uxx (tested with LPC11U14) */ typedef enum { lpc2000_v1, lpc2000_v2, - lpc1700 + lpc1700, + lpc11u, } lpc2000_variant; struct lpc2000_flash_bank { @@ -243,6 +249,34 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) bank->sectors[i].is_erased = -1; bank->sectors[i].is_protected = 1; } + } else if (lpc2000_info->variant == lpc11u) { + lpc2000_info->cmd51_max_buffer = 1024; + + switch (bank->size) { + case 16 * 1024: + bank->num_sectors = 4; + break; + case 24 * 1024: + bank->num_sectors = 6; + break; + case 32 * 1024: + bank->num_sectors = 8; + break; + default: + LOG_ERROR("BUG: unknown bank->size encountered"); + exit(-1); + } + + bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); + + for (int i = 0; i < bank->num_sectors; i++) { + bank->sectors[i].offset = offset; + /* All sectors are 4kB-sized */ + bank->sectors[i].size = 4 * 1024; + offset += bank->sectors[i].size; + bank->sectors[i].is_erased = -1; + bank->sectors[i].is_protected = 1; + } } else { LOG_ERROR("BUG: unknown lpc2000_info->variant encountered"); exit(-1); @@ -273,6 +307,7 @@ static int lpc2000_iap_working_area_init(struct flash_bank *bank, struct working /* write IAP code to working area */ switch (lpc2000_info->variant) { + case lpc11u: case lpc1700: target_buffer_set_u32(target, jump_gate, ARMV4_5_T_BX(12)); target_buffer_set_u32(target, jump_gate + 4, ARMV5_T_BKPT(0)); @@ -307,6 +342,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo uint32_t iap_entry_point = 0; /* to make compiler happier */ switch (lpc2000_info->variant) { + case lpc11u: case lpc1700: armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARMV7M_MODE_ANY; @@ -352,6 +388,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo buf_set_u32(reg_params[2].value, 0, 32, iap_entry_point); switch (lpc2000_info->variant) { + case lpc11u: case lpc1700: /* IAP stack */ init_reg_param(®_params[3], "sp", 32, PARAM_OUT); @@ -481,6 +518,12 @@ FLASH_BANK_COMMAND_HANDLER(lpc2000_flash_bank_command) lpc2000_info->cmd51_can_256b = 1; lpc2000_info->cmd51_can_8192b = 0; lpc2000_info->checksum_vector = 7; + } else if (strcmp(CMD_ARGV[6], "lpc11u") == 0) { + lpc2000_info->variant = lpc11u; + lpc2000_info->cmd51_dst_boundary = 256; + lpc2000_info->cmd51_can_256b = 1; + lpc2000_info->cmd51_can_8192b = 0; + lpc2000_info->checksum_vector = 7; } else { LOG_ERROR("unknown LPC2000 variant: %s", CMD_ARGV[6]); free(lpc2000_info); diff --git a/tcl/target/lpc11u14.cfg b/tcl/target/lpc11u14.cfg new file mode 100644 index 0000000..3bc28e1 --- /dev/null +++ b/tcl/target/lpc11u14.cfg @@ -0,0 +1,18 @@ +# NXP LPC11U14 Cortex-M0 with 32kB Flash and 4kB Local On-Chip SRAM, + +set CHIPNAME lpc11u14 +set CPUTAPID 0x0bb11477 +set CPURAMSIZE 0x1000 +set CPUROMSIZE 0x8000 + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 12000 + +# Include the main configuration file. +source [find target/lpc11uxx_stlink.cfg] diff --git a/tcl/target/lpc11uxx_stlink.cfg b/tcl/target/lpc11uxx_stlink.cfg new file mode 100644 index 0000000..f7eaf58 --- /dev/null +++ b/tcl/target/lpc11uxx_stlink.cfg @@ -0,0 +1,88 @@ +# Main file for NXP LPC11Uxx Cortex-M0 +# +# !!!!!! +# +# This file should not be included directly, rather +# by the lpc11u12.cfg, lpc11u14.cfg, etc. which set the +# needed variables to the appropriate values. +# +# !!!!!! + +# LPC11Uxx chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)." +} + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + set _CCLK 12000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)." +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)." +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)." +} + +if { [info exists TRANSPORT] } { + set _TRANSPORT $TRANSPORT +} else { + set _TRANSPORT stlink_swd +} + +transport select $_TRANSPORT + +stlink newtap $_CHIPNAME cpu -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME + +# The LPC11Uxx devices have 4/6/8kB of SRAM In the ARMv6-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC11Uxx devices have 16/24/32kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc11u $_CCLK calc_checksum + +$_TARGETNAME configure -event reset-init { + # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description + # Bit Symbol Value Description Reset value + # 1:0 MAP Memory map control. 0 + # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. + # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. + # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. + # 31:2 - - Reserved. The value read from a reserved bit is not defined. NA + + mww 0x40048000 0x02 +} -- ------------------------------------------------------------------------------ Keep yourself connected to Go Parallel: BUILD Helping you discover the best ways to construct your parallel projects. http://goparallel.sourceforge.net _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
