This is an automated email from Gerrit.

Spencer Oliver ([email protected]) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/1122

-- gerrit

commit 0154caa652a0d4204cd8a4af5c7496b6f7986b0c
Author: Spencer Oliver <[email protected]>
Date:   Fri Jan 25 15:32:42 2013 +0000

    hla: enable DWT component and fix watchpoints
    
    The makes sure the DWT component is always enabled so that watchpoints
    work as expected.
    
    This does need merging into the existing cortex_m logic, however at the
    moment this is non trivial.
    
    Change-Id: Ic6cccd1badb51f70a2ca8ea9ab6923788a94c1bf
    Signed-off-by: Spencer Oliver <[email protected]>

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 6bd286a..1a95d88 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -339,7 +339,7 @@ static int adapter_debug_entry(struct target *target)
        adapter_load_context(target);
 
        /* make sure we clear the vector catch bit */
-       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0);
+       adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
        r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
        xPSR = buf_get_u32(r->value, 0, 32);
@@ -434,9 +434,9 @@ static int adapter_assert_reset(struct target *target)
 
        /* only set vector catch if halt is requested */
        if (target->reset_halt)
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 
VC_CORERESET);
+               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 
TRCENA|VC_CORERESET);
        else
-               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 
0);
+               adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 
TRCENA);
 
        if (jtag_reset_config & RESET_HAS_SRST) {
                if (!srst_asserted) {
@@ -572,7 +572,7 @@ static int adapter_resume(struct target *target, int 
current,
        resume_pc = buf_get_u32(pc->value, 0, 32);
 
        /* write any user vector flags */
-       res = target_write_u32(target, DCB_DEMCR, armv7m->demcr);
+       res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
        if (res != ERROR_OK)
                return res;
 

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