Please find below my patch for the SAM3 calculations of the PLLA
frequency. If the DIV factor was bigger than 1, the PLLA frequency was
set to 0. The patch below fixes this (tested).
---
src/flash/nor/at91sam3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index be3afb2..d6dedae 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -2399,8 +2399,8 @@ static void sam3_explain_ckgr_plla(struct
sam3_chip *pChip)
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
else if (diva == 0)
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
- else if (diva == 1) {
- pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
+ else if (diva >= 1) {
+ pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq *
(mula + 1) / diva);
LOG_USER("\tPLLA Freq: %3.03f MHz",
_tomhz(pChip->cfg.plla_freq));
}
--
1.7.10.4
- Thomas
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