Hi all,
i have a problem with a debug session on Eclipse using an external NOR flash.
This is my configuration:
I'm using OpenOCD 0.6.1 compiled with FTDI CDM Driver (v. 2.08.28) for Win7.
The JTAG adapter is Flyswatter RevB
The Target is a STA8088 SoC (GNSS receiver by ST) - The core is ARM946e-s
The board is a proprietary ST dev.board (TESEOII-SDB Rev2)
I'm using Eclipse CDT Indigo with ARM Sourcery compiler.
When i start a debug session with NOR flash, everything seems to work: the
target reset, the NOR is flashed and
the breakpoint set in the runtime options of the eclipse works too.
The problem is that any breakpoint set during the debug session is ignored and
also, after few "step into", the debug flow stop working
(behaves as if a "continue" or "run" command is sent to the gdb) but nothing
comes out from the serial.
Probably the program flow was never started.
When i perform a physical reset on the board and start a new debug session
WITHOUT flashing the NOR (ie. with the flash already flashed with the
previously session for example), everything works (breakpoints, step, serial,
etc.)
I suspect that the reset on the board sends a sort of a "flash reset" required
after the flash has been written but i don't know how to emulate the same
behavior on the openOCD cfg file.
I tried to set the clock control reg to force an ARM reset after flash with
this instruction in the cfg:
mmw 0x1200f044 0x0 0x1
reg cpsr 0xd3
but to no avail.
Anyone have any idea how to do?
Exists some special instruction to "reset the flash" ?
The OpenOCD CFG file is this:
# Teseo II sta8088f stack flash SOC
set ADAPTER_SLOW 100
set ADAPTER_FAST 3000
source [find mem_helper.tcl]
adapter_khz $ADAPTER_SLOW
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME sta8088
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x05946041
}
debug_level 0
set trst_wid 10
set trst_del 10
set srst_wid 10
set srst_del 10
#reset_config trst_and_srst separate srst_gates_jtag trst_open_drain
srst_open_drain
#reset_config trst_and_srst srst_pulls_trst trst_push_pull srst_open_drain
reset_config trst_and_srst srst_gates_jtag trst_push_pull srst_push_pull
#reset_config trst_only trst_push_pull
#reset_config srst_only srst_open_drain
adapter_nsrst_assert_width $srst_wid
adapter_nsrst_delay $srst_del
jtag_ntrst_assert_width $trst_wid
jtag_ntrst_delay $trst_del
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id
$_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm946e -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm946e
puts "Target = $_TARGETNAME"
# Flash configuration
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
#flash bank b0 cfi 0x30000000 0x04000000 2 2 $_TARGETNAME
flash bank b0 cfi 0x80000000 0x400000 2 2 $_TARGETNAME
flash banks
gdb_memory_map disable
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# Internal sram memory
#$_TARGETNAME configure -work-area-phys 0x11001c00 -work-area-size 0x400
-work-area-backup 0
gdb_breakpoint_override hard
proc teseo_reset {} {
global trst_wid
global srst_wid
global srst_del
# assert both resets; equivalent to power-on reset
jtag_reset 1 0
sleep $trst_wid
jtag_reset 0 1
# drop TRST after at least 32 cycles
sleep $srst_wid
jtag_reset 0 0
sleep $srst_del
# minimum 32 TCK cycles to wake up the controller
runtest 500
}
# reset processing that works with PXA
proc init_reset {mode} {
teseo_reset
# Teseo sometimes gives wrong CPU Id
# so try again
set initfailed [catch {jtag arp_init}]
if {$initfailed} {
sleep 1000
teseo_reset
jtag arp_init
# jtag arp_init-reset
}
# target state is running but 'C' code still
# thinks it is halt. Issue resume will fix this.
catch {resume}
sleep 10
}
proc jtag_init {} {
# init_reset startup
}
# override from startup.tcl
# to change behavior of reset and issue halt
#
#proc ocd_process_reset { MODE } {
# global in_process_reset
# if {$in_process_reset} {
# set in_process_reset 0
# return -code error "'reset' can not be invoked recursively"
# }
# set in_process_reset 1
# set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
# set in_process_reset 0
# if {$success} {
# return $result
# } else {
# return -code error $result
# }
#}
# override from startup.tcl
# to change behavior of reset and issue halt
#
proc ocd_process_reset_inner { MODE } {
set targets [target names]
# If this target must be halted...
set halt -1
if { 0 == [string compare $MODE halt] } {
set halt 1
}
if { 0 == [string compare $MODE init] } {
set halt 1;
}
if { 0 == [string compare $MODE run ] } {
set halt 0;
}
if { $halt < 0 } {
return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
}
# Target event handlers *might* change which TAPs are enabled
# or disabled, so we fire all of them. But don't issue any
# target "arp_*" commands, which may issue JTAG transactions,
# unless we know the underlying TAP is active.
#
# NOTE: ARP == "Advanced Reset Process" ... "advanced" is
# relative to a previous restrictive scheme
foreach t $targets {
# New event script.
$t invoke-event reset-start
}
# Use TRST or TMS/TCK operations to reset all the tap controllers.
# TAP reset events get reported; they might enable some taps.
init_reset $MODE
# Examine all targets on enabled taps.
foreach t $targets {
if {[jtag tapisenabled [$t cget -chain-position]]} {
$t arp_examine
}
}
# Pass 1 - Now wait for any halt (requested as part of reset
# assert/deassert) to happen. Ideally it takes effect without
# first executing any instructions.
if { $halt } {
foreach t $targets {
if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
continue
}
# Teseo doesn't halt on reset so issue halt here
$t arp_halt
# Wait upto 1 second for target to halt. Why 1sec? Cause
# the JTAG tap reset signal might be hooked to a slow
# resistor/capacitor circuit - and it might take a while
# to charge
# Catch, but ignore any errors.
catch { $t arp_waitstate halted 1000 }
# Did we succeed?
set s [$t curstate]
if { 0 != [string compare $s "halted" ] } {
return -code error [format "TARGET: %s - Not halted" $t]
}
}
}
#Pass 2 - if needed "init"
if { 0 == [string compare init $MODE] } {
foreach t $targets {
if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
continue
}
set err [catch "$t arp_waitstate halted 5000"]
# Did it halt?
if { $err == 0 } {
$t invoke-event reset-init
}
}
}
foreach t $targets {
$t invoke-event reset-end
}
}
proc loadsqi { image_file } {
set blksize 32768
load_image [find target/sqi_loader.axf] 0 elf
set bin_image [find $image_file]
set file_size [exec ls -lH $bin_image | awk "{print \$5}"]
for {set buf_pos 0} {$buf_pos < $file_size} {set buf_pos [expr $buf_pos +
$blksize]} {
set remain [expr $file_size - $buf_pos]
set xfer $blksize
if {$remain < $blksize} {
set xfer $remain
}
mww 0x00100ff8 $buf_pos
mww 0x00100ffc $xfer
load_image $bin_image 0x00101000 bin 0x00101000 $blksize $buf_pos
reg pc 0
reg cpsr 0xd3
bp 0xc00 4
resume 0
puts ">>>>> flashing $xfer bytes at $buf_pos of $file_size ..."
wait_halt 100
}
puts ">>>>> $bin_image $file_size bytes loaded"
}
proc tcmreset { } {
global _TARGETNAME
# disable cache
$_TARGETNAME arm946e cp15 0x02 0
# TCMcfg
mww 0x1200f010 0
# ITCM base: 0, phys size 256K
$_TARGETNAME arm946e cp15 0x33 0x12
# DTCM base: 0x00100000, phys size 256K
$_TARGETNAME arm946e cp15 0x31 0x00100012
# ITCM/DTCM enable
$_TARGETNAME arm946e cp15 0x02 0x00050000
# ITCM: 80KB, DTCM: 176KB
mww 0x1200f010 0x00000001
#mww 0x20010008 0x0000105b
#mww 0x2001000c 0x0fffffff
# ARM_BOOT = APB1 SRAM
mww 0x11002004 0x00000004
# REMAP_EN (Enables ITCM)
mww 0x11002000 0x00000800
puts "tcmreset done"
}
proc norinit { } {
global _TARGETNAME
global ADAPTER_FAST
mww 0x11002004 0x00000004
#manual reset
#mmw 0x11002000 0x8000 0x0
mmw 0x1200f044 0x0 0x1
reg cpsr 0xd3
$_TARGETNAME arm946e cp15 0x02 0x00050078
$_TARGETNAME arm946e cp15 0x33 0x12
$_TARGETNAME arm946e cp15 0x31 0x00100012
# Work_Area TCM
$_TARGETNAME configure -work-area-phys 0x0 -work-area-size 0xFFFF
-work-area-backup 0
# Enable NOR Flash
mww 0x1200f040 0xc00003fb
# Set NOR Flash timing
mww 0x20010000 0x3059
mww 0x20010004 0x0fffffff
puts "NorInit done"
}
proc raminit { } {
global ADAPTER_FAST
# Enable RAM Area
mww 0x20010008 0x0000105b
mww 0x2001000c 0x0fffffff
puts "RamInit done"
#adapter_khz $ADAPTER_FAST
adapter_khz 2000
}
proc sqireset { } {
global _TARGETNAME
global ADAPTER_FAST
tcmreset
#enable SQI
#mww 0x1200f040 0xc00003f7
# Set bit 2, enable SQI Clk
mmw 0x1200f040 0x00000004 0x00000000
# SW_RESET
mww 0x2002010c 0x01000000
# WRSR | SPI mode
mww 0x20020100 0x01030000
# WRSR | SPI mode | EQIQ
mww 0x20020100 0x01030035
sleep 10
# WRSR | 4 dummy cycles | SQIQ mode
mww 0x20020100 0x010b0100
# 4 dummy cycles
mww 0x2002010c 0x00010000
puts "sqireset done"
adapter_khz $ADAPTER_FAST
}
$_TARGETNAME configure -event reset-start {
global ADAPTER_SLOW
puts "Running reset-start script"
# halt
adapter_khz $ADAPTER_SLOW
# sqireset
}
$_TARGETNAME configure -event reset-init {
puts "Running reset-init script"
# sqireset
}
$_TARGETNAME configure -event reset-assert {
puts "Running reset-assert script"
}
$_TARGETNAME configure -event reset-deassert-post {
puts "Running reset-deassert-post"
# sleep 5000
}
$_TARGETNAME configure -event reset-end {
global _TARGETNAME
puts "Running reset-end script"
if { [$_TARGETNAME curstate] == "halted" } {
#sqireset
norinit
raminit
}
}
Thanks in advance.
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