This is an automated email from Gerrit. Oleksij Rempel ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1341
-- gerrit commit f070ee6d90e3cecfdfe7a274c33c2b0ef9c330d0 Author: Oleksij Rempel <[email protected]> Date: Mon Apr 15 07:58:40 2013 +0200 mips_ejtag: remove memory protection bit befor DM Change-Id: Id1564ae063cea4f056b350436d52df5381ca9608 Signed-off-by: Oleksij Rempel <[email protected]> diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index 8de54cc..51d8422 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -28,6 +28,7 @@ #include "mips32.h" #include "mips_ejtag.h" +#include "mips32_dmaacc.h" void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr) { @@ -218,11 +219,41 @@ int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step) return retval; } +/* + * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF + * It is needed by EJTAG 1.5-2.0, espesially for BMIPS CPUs + * For example bcm7401 and others. At leas on some + * CPUs, DebugMode wont start if this bit is not removed. + */ +static int disable_dcr_mp(struct mips_ejtag *ejtag_info) +{ + uint32_t dcr; + int retval; + + retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr); + if (retval != ERROR_OK) + goto error; + + dcr &= ~EJTAG_DCR_MP; + retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr); + if (retval != ERROR_OK) + goto error; + return ERROR_OK; +error: + LOG_ERROR("Failed to remove DCR MPbit!"); + return retval; +} + int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) { uint32_t ejtag_ctrl; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { + if (disable_dcr_mp(ejtag_info) != ERROR_OK) + goto error; + } + /* set debug break bit */ ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); @@ -231,12 +262,13 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl); - if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) { - LOG_ERROR("Failed to enter Debug Mode!"); - return ERROR_FAIL; - } + if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) + goto error; return ERROR_OK; +error: + LOG_ERROR("Failed to enter Debug Mode!"); + return ERROR_FAIL; } int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info) diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index 104edfd..fae6899 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -110,6 +110,7 @@ #define EJTAG_DCR_DB (1 << 17) #define EJTAG_DCR_IB (1 << 16) #define EJTAG_DCR_INTE (1 << 4) +#define EJTAG_DCR_MP (1 << 2) /* breakpoint support */ #define EJTAG_IBS 0xFF301000 -- ------------------------------------------------------------------------------ Precog is a next-generation analytics platform capable of advanced analytics on semi-structured data. The platform includes APIs for building apps and a phenomenal toolset for data science. Developers can use our toolset for easy data analysis & visualization. Get a free account! http://www2.precog.com/precogplatform/slashdotnewsletter _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
